E. New Hardware

• Four new TTL chips:
  • 7410 - 3 three-input NAND
  • 7420 - 2 four-input NAND
  • 7425 - 2 four-input NOR, each with a "strobe".
  • 74163 - synchronous 4-bit(binary) counter

F. Circuit Analysis

• For this lab, you are asked to realize a switching circuit with four inputs.
• To test all combinations of the inputs, you can use the outputs of the synchronous counter.
• You may need to design both SOP and POS forms with as few chips as possible.

• Consider the switching function f(x₄,x₃,x₂,x₁) = m(5, 9, 10, 11, 15) + d(2, 6, 13, 14), shown in Fig. 3.3 along with a minimal covering.
  
  • The SOP result is f = X₁X₄ + X₂X'₁ + X'₂X₁X₃ and
    
    f' = X'₁X'₂ + X₂X'₄ + X'₃X'₄
  • the POS result is f = (X₁ + X₂)(X'₂ + X₄)(X₃ + X₄).
  • The NAND and NOR implementatations are shown in Fig. 3.4 and Fig. 3.5, respectively.
    
  • How many chips are required?
    • The SOP requires
      • 2/6 of a 7404(NOT)
      • 2/4 of a 7400(2-input NAND) and
      • 2/3 of a 7410(3-input NAND).
    • The POS reqires the same number of chips, but one less gate:
      • 1/6 of a 7404,
      • 3/4 of a 7402 and
      • 1/3 pf a 7427.
    • The SOP implementation has a potential problem with gliches.
    • For example,
      • if the current input X₄X₃X₂X₁ = 1011 then the output is one.
      • If X₁ goes to zero (X₄X₃X₂X₁ = 1010),
        the output should remain at one, but a glitch may develop due to the delay through the upper inverter in Fig. 3.4.
        
      • The realization f = X₁X₄ + X₂X₄ + X'₂X₁X₃ will avoid this problem.

G. Helpful Hints

Laboratory 3 Description - Swithcing Circuits and Digital Logic Analyzers

Objective:

• To learn to use a Digital Logic Analyzer as a timing analyzer and
• to build and test SOP and POS realization of various four-variable switching functions.
• To identify glitches and other non-ideal features.

Available Hardware:

• Digital component boxes - see Appencix G.
• In class, you will be told to do one of the following labs: 3A - 3R.
• Look at the table on page 43 for the components and switching function f(X₄, X₃, X₂, X₁) that correspond to your lab.

Pre-lab preparation:

Part I - SOP Design

1. Design a minimum SOP realization of f(X₄, X₃,X₂,X₁) using only TTL NAND gates.
2. Draw the logic diagram and wiring diagram for the circuit.
3. Use PSpice to simulate the SOP circuit and plot the output and the variable signals as a function of time when you use a 74163 to generate the input signals.
   

   Part II - POS Design

4. Design a minimum POS realization of f(X₄, X₃, X₂ X₁) using only TTL NOR gates.
5. Draw the logic diagram and wiring diagram fot the circuit.
6. Use PSpice to simulate the POS circuit and plot the output and the variable signals as a function of time when you use a 74163 to generate the input signals.
   
   See sample logic diagrams, sample wiring diagram, and sample output plots.

   Part III - CMOS POS Design

7. Draw the wiring diagram for the POS circuit using CMOS technology.

   Part IV - CMOS SOP Design

8. Draw the wiring diagram for the SOP circuit using CMOS technology.

Experimental Procedure:

• Bring floppy disks(3 1/2) with you to the lab to store your traces.
• Ask the TA questions regarding any procedures about which you are uncertain.
• Turn off all power supplies any time that you make any change to the circuit.
• DO NOT apply more than 5V to the circuit at any time.
• Arrange your circuit components neatly and in a logical order.
• Compare your breadboards carefully with your circuit diagrams before applying power to the circuit.
• Complete the following tasks:

  Part I - Input variable generation

  1. Use a 74163 synchronous divide-by-16 cunter to provide the variables to test your circuit.
     Disable the load, clear, and hold(not enabled) features of the counter.
  2. Use the Sync Out" connector of the sweep generator, set to 20 kHz, to provide the clock input to the 74163.
  3. Use the oscilloscope to plot the clock and counter outputs simultaneously.
     • Trigger off the clock, and split the oscilloscope screen into four sections,
     • displaying one trace in each section.
     • Measure the delay for each of the outputs(see page 19 for a definition).

     Part II - Switching circuit construction

  4. Construct the switching circuit on your breadboard.
  5. Use the oscilloscope to plot the clock and output pulse. You may have trouble achieving a stable trigger. One poosibility is to set the trigger to: triggered, delay, qualify on state, trigger on count 11. Set the clock number to correspond to the probe channe connecgted to the output signal and adjust the delay to place the zero output at the leftmost part of the screen. Plot the result.
  6. Measure the time delay bewtween the clock and the output signal, as well as the delays between the clock and the intermediate switching circuit signals.

     Part III - Digital logic analyzer

  7. Following the steps outlined in Appendix F, use the digital logic analyzer to plot the output of the circuit, the four input variables, the output signal f(X₄, X₃, X₂, X₁), and as many of the intermediate signals as possible.
  8. Make both a hard copy of the output and a copy of floppy disk. (TIFF files are suggested, but use whatever is most convenient for you.)

Post-lab analyhsis:

• Part I - Input variable generation

• Part II - Switching circuit construction

• Part III - Digital logic analyzer

• Part IV - Advanced Questions