A. Lab Goals

• The main objective of this lab is to design, build and test a synchronous sequential circuit which detects a specific sequence from a single-bit input stream.
  
  
• You will also learn how to use a shift-resister to generate an 8-bit sequence and how to make the control signals necessay to generate and output the sequence.

B. Background Reading

• sequence detectors in section 8.3 of (N/N) or section 6.5 in (M).
  
  
• debouncers on p.658 of (N/N) p. 358 in (M). debouncers on p. 658 of (N/N).
  
  
• latches and flip-flops in Laboratory 5 of the lab manual.

C. Definitions

• Shift register
  
  
• SPDT switch
  
  
• Switch debouncer

D. Laboratory Equipment

• No new equipment for this lab.

E. New Hardware

• 74165 - 8-bit shift register
  

F. Circuit Analysis

• We want to detect a sequence of four consecutive ones.
  
  
• For every new clock pulse, a new input X appears and a new output Z appears.
  
  
• Z will be zero unless the current X and the previous three X's were all ones.
  
  
• Overlap will be allowed, so the input X = 101111101 will result in the output Z = 0000011100.

1. First, we determine the number of states and draw a state diagram.
   
   
2. Then we build the state table and we look to see if any reduction in the number of states is possible.
   
   
3. Based on the type of flip-flops we use, we make transition tables, simplify the circuitry with K maps, and finalize the logic and wiring diagrams.

1. State A is the state we arrive at any time X = 0, because that means we currently have no consecutive ones.
   
   
2. The first "1" brings us to state B with zero output.
   
   
3. The second "1" brings us to state C with zero output, and
   
   
4. the third consecutive "1" brings up to state D with zero output.
   • We should think of states A, B, and C as having 0, 1, and two consecutive ones(11), respectively, but state D as "three or more consecutive ones."
     
     
   • Once in state C, if the next input is X = 1, we stay in state D and output a one.
     
     
   • In any state, if the input is X = 0, we immediately go back to state A and output zero.

• An expanded diagram just for the sequence detedtor is shwon in Fig. 6.5.
  
  
• We will use J-K flip-flops, because they have "don't care" conditions on the inputs that could simplify the switching circuit.

• In Fig. 6.6 we assign the states A - D to specific values of Y₁Y₂ and rewrite the transition table in terms of the flip-flop outputs.
  
  
• The K-map for the output is given in the right of tge fugure.
  
  
• Note that the output is easily expressed as Z = XY₁Y₂.
  
  
  
  
• There are four K-maps required to define the inputs to the flip-flops; they are shown in Fig. 6.7.
  
  
• To arrive at these K-maps we made use of the trransition table for J-K flip-flops shown in Table 6.1.
  
  
  
  
• One possible solution is:
  J₁ = XY₂ = (X' + Y'₂)'
  K₁ = X'
  J₂ = X
  K₂ = Y'₁ + X' = (XY₁)'
  
  
  
  
• One realization of this circuit is shown in Fig. 6.8.
  
  
  
  
  
• The final remaining question is wukk how to load and run the shift register.
  
  
• In previous labs we have used DIP switches and resistors to manually set zeros and ones. That approach will work just fine for the inputs A - H.
  
  
• But control circuitry must be handled differently.
  
  
• When loading, we want (LD)' to be low and CLK INH to be high.
  
  
• Likewise, the reverse must be true when we are running.
  
  A latch, in the configuration shown in Fig. 6.9 effectively debounces the mechanical switch.

Laboratory 5 Description

Objective: