Course Information:
Lecture: | Wed 9:00 - 9:50, CHE-2118 |
Mailing List: | enee245-03all-fall14@coursemail.umd.edu |
Recommended Text: | Smith & Franzon, Verilog Styles for Synthesis of Digital Systems, Prentice Hall |
Instructor Information:
Professor: | Bruce L. Jacob, Electrical & Computer Engineering |
Office: | 1333 A.V. Williams Building |
Phone: | (301) 405-0432 |
Email: | |
Office Hours: | Open-door policy ... |
Teaching Assistants: |
Sec. | Name | Lab Time | Office Hours | |
0301 - | Honglei Li | lihonglei001@gmail.com | Fri 8:00-10:50 | |
0302 - | Ahmed Elshaarany | ahmed.m.elshaarany@ieee.org | Tue 1:00-3:50 | |
0303 - | Xi Chen | daphne2012hust@gmail.com | Thu 8:00-10:50 | |
0304 - | Po-Chun Huang | hpcalex@mail.umd.edu | Fri 11:00-1:50 |
Course Handouts and General Information:
Data Sheets and Equipment Manuals:
Labs:
Lab # | Week of | Topic | Documenation |
0 | Sep 1 | Tutorials on lab equipment & software | PSpice Tutorial.docx
Xilinx Tutorial 1.doc Xilinx Tutorial 2.doc |
1 | Sep 8 | Combinational logic (adders) | Lab1.doc |
2 | Sep 15 | Sequential logic (clocks, registers) | Lab2.docx |
3 | Sep 22 | Simple state machine: saturating counter | Lab3.pdf
DLA.docx datasheets for all the components |
4 | Sep 29 | Intro to MOSFETs and voltage boosting | Lab4.pdf
Lab4-2N7000.pdf |
5 | Oct 6 | Verilog fundamentals | Lab5.pdf
Nexys2_500General.ucf |
6 | Oct 13 | Verilog and FPGA advantages | Lab6.pdf |
7 | Oct 20 | Memory basics: simple controller timing | Lab7.pdf
debouncer.v |
8 | Oct 27 | Memory and DDR I/O timing | Lab8.pdf
debouncer.v MEM_block.v |
9 | Nov 3 | Memory and I/O timing | Lab9.pdf
debouncer.v MEM_block.v |
10 | Nov 10 | LCD Controller & Debugging | Lab10.pdf
LCD_sample_code.zip debouncer.v MEM_block_8bit.v |