ENEE 359V Advanced Digital Design with Hardware Description Languages by P. Petrov

Fall 2009

Class Information

Instructor: Peter Petrov, AVW 1421, ppetrov at ece dot umd dot edu
Class hours: Tu 3:30pm - 4:45pm, EGR 3114
Lab hours: Wed 3:00pm - 5:00pm, AVW 2446
Office hours: Tu/Wed 12:00pm - 1:00pm, AVW 1421
Required text: "Advanced Digital Design with the Verilog HDL", by M. Ciletti

Course Syllabus

Final project information
VGA reference specification for those of you working on a project involving the VGA interface.
RS232-UART reference specification for those of you working on a project involving the serial interface (RS-232) and UART functionality.
Practice problems for the final exam to be held on December 14 (Monday), AVW 2328, 3:00pm - 5:00pm.
Lab assignments:

We will use these two Verilog files for our very first lab exercise: Add_rca_4_Unit_Delay.v , t_Add_rca_4_Unit_Delay.v

Lab assignment, 09/16.
We will work on this assignment in the Lab on 09/16. Students are asked to work on it and develop their own solutions. The instructor will discuss the solution towards the end of the lab session.
The following FPGA pin mapping file test_nexys2.ucf and test Verilog file test_nexys2.v were discussed in the lab and will be useful for your designs.
The solution of this assignment is described in LA-1_sol.pdf and the Verilog implementation code is in LA2-Sol.v .

Lab assignment, 09/23.
RTL design and implementation of sequentlial uinsigned binary multiplier. This assignment illustrates the steps invlovled in structruing a complex design. It also demonstrates how to separate and identify the "control" and the "datapath".
A design solution: mult-serial.v

Lab assignment, 10/07.
Design and implementation of a FIFO buffer.
A design solution: fifo1.v. Note that this design does not allow overlapping operations and that each operation takes two clock cycles.
During the lab on 10/14, we will design and test a FIFO capable of simultaneous insert/remove operations with a throughput of single clock cycle per operation.
A design solution: fifo2.v. And a test-bench file: fifo_test.v

Lab assignment, 10/28
Implementation and analysis of Finate State Machines (FSM).

Lab assignment, 11/04
Design and Implementation of Restoring and Non-Restoring division algorithms.

Lab assignment, 11/18
Error Detecting and Correcting Hamming Codes
Project assignments:

Project-1 (15%). Decimal calculator
Assigned: Monday, Sep 14; Due: Tuesday Sep 29
You can use in your project these binary-to-bcd and bcd-to-binary conversion Verilog modules.
A design solution for Project1: P1-Sol.v

Project-2 (15%). Booth multiplier
Assigned: Monday, Oct 5; Due: Monday, Oct 26
A design solution for Project2: P2-Sol.v and booth.v.
Lecture notes:

ASIC/FPGA Design Flow. Structural Modeling with Verilog. Primitives and Modules. [pdf]
Logic Design with Behavioral Models. Continous Assignments and Cyclic Behaviors. Register Transfer Level (RTL) modeling. [pdf]
Machines with Repetitive and Multicycle Behavior; Tasks and Functions in Verilog. [pdf]
Algorithmic State Machine and Datapath Charts (ASM, ASMD) [pdf]
Metastability and Synchronizers. Design example: Keypad Scanner and Encoder [pdf]
Booth's multiplication algorithm. [pdf]
Verilog Constructs/Styles and their Synthesis; Logic, RTL, and High-Level Synthesis; Synthesis of Combinational Logic. [pdf]
Synthesis of Three-State Devices. Synthesis of Sequential Logic with Flip-Flops [pdf]
Modeling and Synthesis of Finite State Machines - Explicit and Implicit styles; Registered Outputs [pdf]
Anticipating Results of Synthesis; Data Types, Expressions, and Loops [pdf]
Design and Synthesis of Datapath Controllers; RISC Stored-Program Machines [pdf]
Pipelined Architectures; Circular Buffers; Communication Across Clock Domains [pdf]
Complex Programmable Logic and Storage Devices; FPGA Architectures [pdf]

Course Work, Policies, and Grading

There will be 2 (two) term project assignments and 1 (one) final project assignment. The projects will be implemented on an FPGA board. For this, students are required to purchase the Digilent Nexys2 FPGA development board: http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2. The version with 500K gates FPGA chip will be sufficient for this class. Note that this board is used in other ECE classes as well.

Lab exercises and projects will be implemented using the freely available ISE WebPack software from Xilinx. It offers design capture, simulation, and synthesis functions. The software can be downloaded from http://www.xilinx.com/tools/webpack.htm.

The class will have a final exam. The final exam will be based entirely on the course material and the project assignments; it will be closed book, closed notes. The final grade will be formed as follows:

Project 1 (Sept. 29) : 15%
Project 2 (Oct. 26) : 15%
Final Project (Dec. 18) : 35%
Lab participation : 5%
Final exam (December 14, Monday, AVW 2328, 3:00pm - 5:00pm): 30%