// // The RiSC-32 (32-bit Ridiculously Simple Core) // // // 2 pipelines // 2 RF write ports // 4 RF read ports // - 16-entry 32-bit scalar register file // - 16-entry 128-bit vector register file // 2 SRAM ports // // // OPCODES // `define OP_add 4'd0 `define OP_addi 4'd1 `define OP_and 4'd2 `define OP_mul 4'd3 `define OP_sub 4'd4 `define OP_lw 4'd5 `define OP_sw 4'd6 `define OP_bne 4'd7 `define OP_blz 4'd7 `define OP_vadd 4'd8 `define OP_vsum 4'd9 `define OP_vand 4'd10 `define OP_vmul 4'd11 `define OP_vxor 4'd12 `define OP_vlw 4'd13 `define OP_vmov 4'd14 `define OP_vsw 4'd14 `define OP_jalr 4'd15 `define OP_ext 4'd15 // // SUB-OPCODES // `define CTL_vec 4'd0 `define CTL_vlo 4'd1 `define CTL_vhi 4'd2 // // SYSTEM OPCODES // `define SYSOP_mode 4'd1 `define SYSOP_rfe 4'd2 `define SYSOP_bpred 4'd3 // // INSTRUCTION FIELDS // `define pipe0_op 31:28 `define pipe0_ra 27:24 `define pipe0_rb 23:20 `define pipe0_rci 19:16 `define pipe0_rci_topbit 19 `define pipe1_op 15:12 `define pipe1_ra 11:8 `define pipe1_rb 7:4 `define pipe1_rci 3:0 `define pipe1_rci_topbit 3 `define pipe1_blz_rci 7:0 `define pipe1_blz_rci_topbit 7 // // ETC // `define TRUE 1'd1 `define FALSE 1'd0 `define ZERO 32'd0 `define REGZERO 5'd0 `define OPZ 4'bZ `define REGZ 4'bZ `define MEMZ 16'bZ `define DATAZ 128'bZ `define DEADVAL 128'h1010101feeddeadbeef2b0b // // CORE // module RiSC32 (clk, reset); input clk; input reset; // // clock tree, reset tree, write-enable tree // wire we = 1; wire clk_PC, clk_IFID, clk_IFIDpc, clk_IDEXpc, clk_EXWBpc, clk_BP, clk_RF, clk_MEM; buf bufclkPC(clk_PC, clk), bufclkIFID(clk_IFID, clk), bufclkIFIDpc(clk_IFIDpc, clk), bufclkIDEXpc(clk_IDEXpc, clk), bufclkEXWBpc(clk_EXWBpc, clk), bufclkBP(clk_BP, clk), bufclkRF(clk_RF, clk), bufclkMEM(clk_MEM, clk); wire reset_PC, reset_IFID, reset_IFIDpc, reset_IDEXpc, reset_EXWBpc, reset_BP, reset_RF, reset_MEM; buf bufresetPC(reset_PC, reset), bufresetIFID(reset_IFID, reset), bufresetIFIDpc(reset_IFIDpc, reset), bufresetIDEXpc(reset_IDEXpc, reset), bufresetEXWBpc(reset_EXWBpc, reset), bufresetBP(reset_BP, reset), bufresetRF(reset_RF, reset), bufresetMEM(reset_MEM, reset); wire we_PC, we_IFID, we_IFIDpc, we_IDEXpc, we_EXWBpc; buf bufwePC(we_PC, we), bufweIFID(we_IFID, we), bufweIFIDpc(we_IFIDpc, we), bufweIDEXpc(we_IDEXpc, we), bufweEXWBpc(we_EXWBpc, we); wire clk_IDEX_1, clk_EXWB_1, clk_IDEX_2, clk_EXWB_2; buf bufclkIDEX_1(clk_IDEX_1, clk), bufclkEXWB_1(clk_EXWB_1, clk), bufclkIDEX_2(clk_IDEX_2, clk), bufclkEXWB_2(clk_EXWB_2, clk); wire reset_IDEX_1, reset_EXWB_1, reset_IDEX_2, reset_EXWB_2; buf bufresetIDEX_1(reset_IDEX_1, reset), bufresetEXWB_1(reset_EXWB_1, reset), bufresetIDEX_2(reset_IDEX_2, reset), bufresetEXWB_2(reset_EXWB_2, reset); wire we_IDEX_1, we_EXWB_1, we_IDEX_2, we_EXWB_2; buf bufweIDEX_1(we_IDEX_1, we), bufweEXWB_1(we_EXWB_1, we), bufweIDEX_2(we_IDEX_2, we), bufweEXWB_2(we_EXWB_2, we); // // PIPELINE-REGISTER WIRES // wire [31:0] PC_pc__in = MUX_PC_update; wire [31:0] PC_pc__out; wire [31:0] IFID_pc__in; wire [31:0] IFID_pc__out; wire [3:0] IFID_exc__in; wire [3:0] IFID_exc__out; wire [31:0] IFID_instr__in; wire [31:0] IFID_instr__out; wire [31:0] IDEX_pc__in; wire [31:0] IDEX_pc__out; wire [3:0] IDEX_exc__in; wire [3:0] IDEX_exc__out; wire [127:0] IDEX_arg1_0__in; wire [127:0] IDEX_arg1_0__out; wire [127:0] IDEX_arg2_0__in; wire [127:0] IDEX_arg2_0__out; wire [31:0] IDEX_arg3_0__in; wire [31:0] IDEX_arg3_0__out; wire [4:0] IDEX_op_0__in; wire [4:0] IDEX_op_0__out; wire [4:0] IDEX_rT_0__in; wire [4:0] IDEX_rT_0__out; wire [4:0] IDEX_src1_0__in; wire [4:0] IDEX_src1_0__out; wire [4:0] IDEX_src2_0__in; wire [4:0] IDEX_src2_0__out; wire [127:0] IDEX_arg1_1__in; wire [127:0] IDEX_arg1_1__out; wire [127:0] IDEX_arg2_1__in; wire [127:0] IDEX_arg2_1__out; wire [31:0] IDEX_arg3_1__in; wire [31:0] IDEX_arg3_1__out; wire [4:0] IDEX_op_1__in; wire [4:0] IDEX_op_1__out; wire [4:0] IDEX_rT_1__in; wire [4:0] IDEX_rT_1__out; wire [4:0] IDEX_src1_1__in; wire [4:0] IDEX_src1_1__out; wire [4:0] IDEX_src2_1__in; wire [4:0] IDEX_src2_1__out; wire [31:0] EXWB_pc__in; wire [31:0] EXWB_pc__out; wire [3:0] EXWB_exc__in; wire [3:0] EXWB_exc__out; wire [127:0] EXWB_result_0__in; wire [127:0] EXWB_result_0__out; wire [4:0] EXWB_rT_0__in; wire [4:0] EXWB_rT_0__out; wire [127:0] EXWB_result_1__in; wire [127:0] EXWB_result_1__out; wire [4:0] EXWB_rT_1__in; wire [4:0] EXWB_rT_1__out; wire [4:0] ALU_op_0__in; wire [127:0] ALU_alu1_0__in; wire [127:0] ALU_alu2_0__in; wire [127:0] ALU_bus_0__out; wire [4:0] ALU_op_1__in; wire [127:0] ALU_alu1_1__in; wire [127:0] ALU_alu2_1__in; wire [127:0] ALU_bus_1__out; wire [31:0] BRTEST_arg1_0__in; wire [31:0] BRTEST_arg2_0__in; wire BRTEST_bne_out_0__out; wire [31:0] BRTEST_arg1_1__in; wire [31:0] BRTEST_arg2_1__in; wire BRTEST_blz_out_1__out; wire [31:0] BP_pc__in; wire [31:0] BP_instr__in; wire [31:0] BP_pcPrev__in; wire [31:0] BP_instrPrev__in; wire [31:0] BP_pred__out; wire [4:0] RF_raddr_1__in; wire [4:0] RF_raddr_2__in; wire [4:0] RF_raddr_3__in; wire [4:0] RF_raddr_4__in; wire [127:0] RF_rdata_1__out; wire [127:0] RF_rdata_2__out; wire [127:0] RF_rdata_3__out; wire [127:0] RF_rdata_4__out; wire [4:0] RF_waddr_1__in; wire [4:0] RF_waddr_2__in; wire [127:0] RF_wdata_1__in; wire [127:0] RF_wdata_2__in; wire MEM_re_1__in; wire MEM_re_2__in; wire MEM_we_1__in; wire MEM_we_2__in; wire MEM_vec_1__in; wire MEM_vec_2__in; wire [15:0] MEM_addr_1__in; wire [15:0] MEM_addr_2__in; wire [127:0] MEM_data_1__io; wire [127:0] MEM_data_2__io; wire MEM_fe__in; wire [15:0] MEM_faddr__in; wire [31:0] MEM_fdata__out; // // ADDITIONAL WIRES // wire Pstomp; wire LGimm; wire [31:0] MUX_PC_update; wire [127:0] MUX_EX_fwd1_0__out; wire [127:0] MUX_EX_fwd2_0__out; wire [127:0] MUX_EX_alu2_0__out; wire [127:0] MUX_EX_link_0__out; wire [127:0] MUX_EX_resultMux_0__out; wire [127:0] MUX_EX_fwd1_1__out; wire [127:0] MUX_EX_fwd2_1__out; wire [127:0] MUX_EX_alu2_1__out; wire [127:0] MUX_EX_link_1__out; wire [127:0] MUX_EX_resultMux_1__out; wire [3:0] op_0 = IFID_instr__out[`pipe0_op]; wire [3:0] rA_0 = IFID_instr__out[`pipe0_ra]; wire [3:0] rB_0 = IFID_instr__out[`pipe0_rb]; wire [3:0] rC_0 = IFID_instr__out[`pipe0_rci]; wire [3:0] im_0 = IFID_instr__out[`pipe0_rci]; wire sb_0 = IFID_instr__out[`pipe0_rci_topbit]; wire [3:0] op_1 = IFID_instr__out[`pipe1_op]; wire [3:0] rA_1 = IFID_instr__out[`pipe1_ra]; wire [3:0] rB_1 = IFID_instr__out[`pipe1_rb]; wire [3:0] rC_1 = IFID_instr__out[`pipe1_rci]; wire [3:0] im_1 = IFID_instr__out[`pipe1_rci]; wire sb_1 = IFID_instr__out[`pipe1_rci_topbit]; wire [7:0] blz_im_1 = IFID_instr__out[`pipe1_blz_rci]; wire blz_sb_1 = IFID_instr__out[`pipe1_blz_rci_topbit]; // // MODULE INSTANCES // branch_checker BRTEST1 ( .arg1(BRTEST_arg1_0__in), .arg2(BRTEST_arg2_0__in), .bne_out(BRTEST_bne_out_0__out)); branch_checker BRTEST2 ( .arg1(BRTEST_arg1_1__in), .arg2(BRTEST_arg2_1__in), .blz_out(BRTEST_blz_out_1__out)); combined_ALU ALU1 ( .op5(ALU_op_0__in), .alu1(ALU_alu1_0__in), .alu2(ALU_alu2_0__in), .bus(ALU_bus_0__out)); combined_ALU ALU2 ( .op5(ALU_op_1__in), .alu1(ALU_alu1_1__in), .alu2(ALU_alu2_1__in), .bus(ALU_bus_1__out)); branch_prediction BP ( .pc(BP_pc__in), .instr(BP_instr__in), .pcPrev(BP_pcPrev__in), .instrPrev(BP_instrPrev__in), .pred(BP_pred__out)); register_file RF ( .raddr_1(RF_raddr_1__in), .raddr_2(RF_raddr_2__in), .raddr_3(RF_raddr_3__in), .raddr_4(RF_raddr_4__in), .rdata_1(RF_rdata_1__out), .rdata_2(RF_rdata_2__out), .rdata_3(RF_rdata_3__out), .rdata_4(RF_rdata_4__out), .waddr_1(RF_waddr_1__in), .waddr_2(RF_waddr_2__in), .wdata_1(RF_wdata_1__in), .wdata_2(RF_wdata_2__in), .clk(clk_RF), .reset(reset_RF)); SRAM_block MEM ( .re_1(MEM_re_1__in), .re_2(MEM_re_2__in), .we_1(MEM_we_1__in), .we_2(MEM_we_2__in), .addr_1(MEM_addr_1__in), .addr_2(MEM_addr_2__in), .vec_1(MEM_vec_1__in), .vec_2(MEM_vec_2__in), .data_1(MEM_data_1__io), .data_2(MEM_data_2__io), .fe_1(MEM_fe__in), .faddr_1(MEM_faddr__in), .fdata_1(MEM_fdata__out), .clk(clk_MEM), .reset(reset_MEM)); PC inst_PC ( .PC_pc__in(PC_pc__in), .PC_pc__out(PC_pc__out), .clk(clk_PC), .reset(reset_PC), .we(we_PC)); PC_EXC pcexc_IFID ( .PCEXC_exc__in(IFID_exc__in), .PCEXC_exc__out(IFID_exc__out), .PCEXC_pc__in(IFID_pc__in), .PCEXC_pc__out(IFID_pc__out), .clk(clk_IFIDpc), .reset(reset_IFIDpc | Pstomp), .we(we_IFIDpc)); IFID inst_IFID ( .IFID_instr__in(IFID_instr__in), .IFID_instr__out(IFID_instr__out), .clk(clk_IFID), .reset(reset_IFID | Pstomp), .we(we_IFID)); PC_EXC pcexc_IDEX ( .PCEXC_exc__in(IDEX_exc__in), .PCEXC_exc__out(IDEX_exc__out), .PCEXC_pc__in(IDEX_pc__in), .PCEXC_pc__out(IDEX_pc__out), .clk(clk_IDEXpc), .reset(reset_IDEXpc | Pstomp | LGimm), .we(we_IDEXpc)); IDEX inst_IDEX_1 ( .IDEX_arg1__in(IDEX_arg1_0__in), .IDEX_arg1__out(IDEX_arg1_0__out), .IDEX_arg2__in(IDEX_arg2_0__in), .IDEX_arg2__out(IDEX_arg2_0__out), .IDEX_arg3__in(IDEX_arg3_0__in), .IDEX_arg3__out(IDEX_arg3_0__out), .IDEX_op__in(IDEX_op_0__in), .IDEX_op__out(IDEX_op_0__out), .IDEX_rT__in(IDEX_rT_0__in), .IDEX_rT__out(IDEX_rT_0__out), .IDEX_src1__in(IDEX_src1_0__in), .IDEX_src1__out(IDEX_src1_0__out), .IDEX_src2__in(IDEX_src2_0__in), .IDEX_src2__out(IDEX_src2_0__out), .clk(clk_IDEX_1), .reset(reset_IDEX_1 | Pstomp | LGimm), .we(we_IDEX_1)); IDEX inst_IDEX_2 ( .IDEX_arg1__in(IDEX_arg1_1__in), .IDEX_arg1__out(IDEX_arg1_1__out), .IDEX_arg2__in(IDEX_arg2_1__in), .IDEX_arg2__out(IDEX_arg2_1__out), .IDEX_arg3__in(IDEX_arg3_1__in), .IDEX_arg3__out(IDEX_arg3_1__out), .IDEX_op__in(IDEX_op_1__in), .IDEX_op__out(IDEX_op_1__out), .IDEX_rT__in(IDEX_rT_1__in), .IDEX_rT__out(IDEX_rT_1__out), .IDEX_src1__in(IDEX_src1_1__in), .IDEX_src1__out(IDEX_src1_1__out), .IDEX_src2__in(IDEX_src2_1__in), .IDEX_src2__out(IDEX_src2_1__out), .clk(clk_IDEX_2), .reset(reset_IDEX_2 | Pstomp | LGimm), .we(we_IDEX_2)); PC_EXC pcexc_EXWB ( .PCEXC_exc__in(EXWB_exc__in), .PCEXC_exc__out(EXWB_exc__out), .PCEXC_pc__in(EXWB_pc__in), .PCEXC_pc__out(EXWB_pc__out), .clk(clk_EXWBpc), .reset(reset_EXWBpc), .we(we_EXWBpc)); EXWB inst_EXWB_1 ( .EXWB_rfdata__in(EXWB_result_0__in), .EXWB_rfdata__out(EXWB_result_0__out), .EXWB_rT__in(EXWB_rT_0__in), .EXWB_rT__out(EXWB_rT_0__out), .clk(clk_EXWB_1), .reset(reset_EXWB_1), .we(we_EXWB_1)); EXWB inst_EXWB_2 ( .EXWB_rfdata__in(EXWB_result_1__in), .EXWB_rfdata__out(EXWB_result_1__out), .EXWB_rT__in(EXWB_rT_1__in), .EXWB_rT__out(EXWB_rT_1__out), .clk(clk_EXWB_2), .reset(reset_EXWB_2), .we(we_EXWB_2)); ///////////////////////// // INSTRUCTION FETCH ///////////////////////// assign IFID_instr__in = MEM_fdata__out; assign IFID_pc__in = PC_pc__out; assign MEM_fe__in = 1; assign MEM_faddr__in = PC_pc__out[15:0]; // this would be modified to check for errors assign IFID_exc__in = 4'd0; // // Branch Predictor inputs // assign BP_pc__in = PC_pc__out; assign BP_instr__in = MEM_fdata__out; assign BP_pcPrev__in = IFID_pc__out; assign BP_instrPrev__in = IFID_instr__out; ///////////////////////// // INSTRUCTION DECODE ///////////////////////// wire ifid_0_has_add = (op_0 == `OP_add); wire ifid_0_has_addi = (op_0 == `OP_addi); wire ifid_0_has_and = (op_0 == `OP_and); wire ifid_0_has_mul = (op_0 == `OP_mul); wire ifid_0_has_sub = (op_0 == `OP_sub); wire ifid_0_has_lw = (op_0 == `OP_lw); wire ifid_0_has_sw = (op_0 == `OP_sw); wire ifid_0_has_bne = (op_0 == `OP_bne); wire ifid_0_has_vadd = (op_0 == `OP_vadd); wire ifid_0_has_vsum = (op_0 == `OP_vsum); wire ifid_0_has_vand = (op_0 == `OP_vand); wire ifid_0_has_vmul = (op_0 == `OP_vmul); wire ifid_0_has_vxor = (op_0 == `OP_vxor); wire ifid_0_has_vlw = (op_0 == `OP_vlw); wire ifid_0_has_vmov = (op_0 == `OP_vmov); wire ifid_0_has_jalr = (op_0 == `OP_jalr); wire ifid_0_has_ext = (op_0 == `OP_ext); wire ifid_1_has_add = (op_1 == `OP_add); wire ifid_1_has_addi = (op_1 == `OP_addi); wire ifid_1_has_and = (op_1 == `OP_and); wire ifid_1_has_mul = (op_1 == `OP_mul); wire ifid_1_has_sub = (op_1 == `OP_sub); wire ifid_1_has_lw = (op_1 == `OP_lw); wire ifid_1_has_sw = (op_1 == `OP_sw); wire ifid_1_has_blz = (op_1 == `OP_blz); wire ifid_1_has_vadd = (op_1 == `OP_vadd); wire ifid_1_has_vsum = (op_1 == `OP_vsum); wire ifid_1_has_vand = (op_1 == `OP_vand); wire ifid_1_has_vmul = (op_1 == `OP_vmul); wire ifid_1_has_vxor = (op_1 == `OP_vxor); wire ifid_1_has_vlw = (op_1 == `OP_vlw); wire ifid_1_has_vsw = (op_1 == `OP_vsw); wire ifid_1_has_jalr = (op_1 == `OP_jalr); wire ifid_1_has_ext = (op_1 == `OP_ext); wire ifid_1_has_vec = ifid_0_has_vmov & (op_1 == `CTL_vec); wire ifid_1_has_vlo = ifid_0_has_vmov & (op_1 == `CTL_vlo); wire ifid_1_has_vhi = ifid_0_has_vmov & (op_1 == `CTL_vhi); // // Put Immediate Values into ARG3 // assign IDEX_arg3_0__in = assign IDEX_arg3_1__in = // // Set OP and RT // wire ifid_0_no_RFwrite = wire ifid_1_no_RFwrite = assign IDEX_op_0__in = assign IDEX_op_1__in = wire ifid_0_writesVRF = (ifid_0_has_vadd | ifid_0_has_vand | ifid_0_has_vmul | ifid_0_has_vxor | ifid_0_has_vlw | ifid_1_has_vec); wire ifid_1_writesVRF = (ifid_1_has_vadd | ifid_1_has_vand | ifid_1_has_vmul | ifid_1_has_vxor | ifid_1_has_vlw); assign IDEX_rT_0__in = assign IDEX_rT_1__in = // // Set SRC1 and SRC2 fields, ARG1 and ARG2 values // wire ifid_0_readsVRF = (ifid_0_has_vadd | ifid_0_has_vsum | ifid_0_has_vand | ifid_0_has_vmul | ifid_0_has_vxor | (ifid_0_has_vmov & (ifid_1_has_vlo | ifid_1_has_vhi))); wire ifid_1_readsVRF = (ifid_1_has_vadd | ifid_1_has_vsum | ifid_1_has_vand | ifid_1_has_vmul | ifid_1_has_vxor | ifid_1_has_vsw | (ifid_0_has_vmov & (ifid_1_has_vlo | ifid_1_has_vhi))); assign IDEX_src1_0__in = assign IDEX_src1_1__in = assign IDEX_src2_0__in = assign IDEX_src2_1__in = assign RF_raddr_1__in = assign RF_raddr_2__in = assign RF_raddr_3__in = assign RF_raddr_4__in = assign IDEX_arg1_0__in = assign IDEX_arg2_0__in = assign IDEX_arg1_1__in = assign IDEX_arg2_1__in = // // set the EXC register // assign IDEX_pc__in = assign IDEX_exc__in = ///////////////////////// // INSTRUCTION EXECUTE ///////////////////////// wire idex_0_has_add = (IDEX_op_0__out[3:0] == `OP_add); wire idex_0_has_addi = (IDEX_op_0__out[3:0] == `OP_addi); wire idex_0_has_and = (IDEX_op_0__out[3:0] == `OP_and); wire idex_0_has_mul = (IDEX_op_0__out[3:0] == `OP_mul); wire idex_0_has_sub = (IDEX_op_0__out[3:0] == `OP_sub); wire idex_0_has_lw = (IDEX_op_0__out[3:0] == `OP_lw); wire idex_0_has_sw = (IDEX_op_0__out[3:0] == `OP_sw); wire idex_0_has_bne = (IDEX_op_0__out[3:0] == `OP_bne); wire idex_0_has_vadd = (IDEX_op_0__out[3:0] == `OP_vadd); wire idex_0_has_vsum = (IDEX_op_0__out[3:0] == `OP_vsum); wire idex_0_has_vand = (IDEX_op_0__out[3:0] == `OP_vand); wire idex_0_has_vmul = (IDEX_op_0__out[3:0] == `OP_vmul); wire idex_0_has_vxor = (IDEX_op_0__out[3:0] == `OP_vxor); wire idex_0_has_vlw = (IDEX_op_0__out[3:0] == `OP_vlw); wire idex_0_has_vmov = (IDEX_op_0__out[3:0] == `OP_vmov); wire idex_0_has_jalr = (IDEX_op_0__out[3:0] == `OP_jalr); wire idex_1_has_add = (IDEX_op_1__out[3:0] == `OP_add); wire idex_1_has_addi = (IDEX_op_1__out[3:0] == `OP_addi); wire idex_1_has_and = (IDEX_op_1__out[3:0] == `OP_and); wire idex_1_has_mul = (IDEX_op_1__out[3:0] == `OP_mul); wire idex_1_has_sub = (IDEX_op_1__out[3:0] == `OP_sub); wire idex_1_has_lw = (IDEX_op_1__out[3:0] == `OP_lw); wire idex_1_has_sw = (IDEX_op_1__out[3:0] == `OP_sw); wire idex_1_has_blz = (IDEX_op_1__out[3:0] == `OP_blz); wire idex_1_has_vadd = (IDEX_op_1__out[3:0] == `OP_vadd); wire idex_1_has_vsum = (IDEX_op_1__out[3:0] == `OP_vsum); wire idex_1_has_vand = (IDEX_op_1__out[3:0] == `OP_vand); wire idex_1_has_vmul = (IDEX_op_1__out[3:0] == `OP_vmul); wire idex_1_has_vxor = (IDEX_op_1__out[3:0] == `OP_vxor); wire idex_1_has_vlw = (IDEX_op_1__out[3:0] == `OP_vlw); wire idex_1_has_vsw = (IDEX_op_1__out[3:0] == `OP_vsw); wire idex_1_has_jalr = (IDEX_op_1__out[3:0] == `OP_jalr); wire idex_has_vec = (IDEX_op_1__out == {1'b1, `CTL_vec}); wire idex_has_vlo = (IDEX_op_1__out == {1'b1, `CTL_vlo}); wire idex_has_vhi = (IDEX_op_1__out == {1'b1, `CTL_vhi}); // // PC UPDATE // // this could be put anywhere, but a lot of it depends on // what's going on in the EXECUTE stage (JALR, BNE, BLZ), // so that's why it happened to end up here ... // // // Handle case when a JALR is in EX // wire [31:0] jump_addr = wire idex_has_jump = idex_0_has_jalr | idex_1_has_jalr; // // Handle branch resolution // - it is a forward branch and it IS taken // - it is a backward branch and it IS NOT taken // wire idex_has_branch = idex_0_has_bne | idex_1_has_blz; // where does the BRANCH say to go next? wire [31:0] idex_brOffset = wire [31:0] idex_pcNext = wire [31:0] actual_pcNext = // does the branch outcome equal where we actually went? wire idex_mispredict = // Handle all of the cases: // - jump takes precedence // - taken branch wins in left-v-right // - otherwise, default assign MUX_PC_update = assign Pstomp = idex_has_jump | idex_mispredict; // // INSTRUCTION EXECUTION // // the instruction in IDEX uses a large-form immediate value wire idex_0_largeImm = wire idex_1_largeImm = wire idex_largeImm = idex_0_largeImm | idex_1_largeImm; assign LGimm = idex_largeImm; // // Forwarding Logic, ALU-input MUX // wire idex_0_src1_iszero = assign MUX_EX_fwd1_0__out = wire idex_0_src2_iszero = assign MUX_EX_fwd2_0__out = wire idex_0_usesImm = assign MUX_EX_alu2_0__out = assign MUX_EX_link_0__out = wire idex_1_src1_iszero = assign MUX_EX_fwd1_1__out = wire idex_1_src2_iszero = assign MUX_EX_fwd2_1__out = wire idex_1_usesImm = assign MUX_EX_alu2_1__out = assign MUX_EX_link_1__out = // // ALU inputs // assign ALU_op_0__in = IDEX_op_0__out; // this is a trick to get the ALU to do what I wanted it to do ... assign ALU_op_1__in = (idex_has_vlo | idex_has_vhi) ? (IDEX_op_1__out | 4'b1000) : IDEX_op_1__out; assign ALU_alu1_0__in = assign ALU_alu2_0__in = assign ALU_alu1_1__in = assign ALU_alu2_1__in = assign BRTEST_arg1_0__in = assign BRTEST_arg2_0__in = assign BRTEST_arg1_1__in = assign BRTEST_arg2_1__in = // // MEM inputs // assign MEM_re_1__in = assign MEM_we_1__in = assign MEM_vec_1__in = assign MEM_addr_1__in = ALU_bus_0__out[15:0]; assign MEM_re_2__in = assign MEM_we_2__in = assign MEM_vec_2__in = assign MEM_addr_2__in = ALU_bus_1__out[15:0]; // the memory-data bus is driven on SW instructions, Hi-Z otherwise (this is how to handle bi-directional busses) assign MEM_data_1__io = (MEM_we_1__in) ? MUX_EX_fwd2_0__out : 128'bZ; assign MEM_data_2__io = (MEM_we_2__in) ? MUX_EX_fwd2_1__out : 128'bZ; // // inputs to EXWB // assign EXWB_pc__in = assign EXWB_exc__in = assign EXWB_rT_0__in = assign EXWB_rT_1__in = assign EXWB_result_0__in = assign EXWB_result_1__in = // these implement the "result_0" and "result_1" muxes assign MUX_EX_resultMux_0__out = assign MUX_EX_resultMux_1__out = ///////////////////////// // INSTRUCTION WRITEBACK ///////////////////////// assign RF_waddr_1__in = assign RF_waddr_2__in = assign RF_wdata_1__in = assign RF_wdata_2__in = always @(posedge clk) begin // // put whatever $display statements you want here // if (EXWB_exc__out != 4'd0) $finish; end endmodule