`define ZERO32 32'h0 `define ZERO4 4'h0 `define ZERO128 128'h0 module register_file ( raddr_1, raddr_2, raddr_3, raddr_4, rdata_1, rdata_2, rdata_3, rdata_4, waddr_1, waddr_2, wdata_1, wdata_2, reset, clk ); input [4:0] raddr_1; input [4:0] raddr_2; input [4:0] raddr_3; input [4:0] raddr_4; output [127:0] rdata_1; output [127:0] rdata_2; output [127:0] rdata_3; output [127:0] rdata_4; input [4:0] waddr_1; input [4:0] waddr_2; input [127:0] wdata_1; input [127:0] wdata_2; input reset; input clk; wire [31:0] srf_data_1, srf_data_2, srf_data_3, srf_data_4; wire [3:0] srf_waddr_1 = (waddr_1[4]) ? `ZERO4 : waddr_1[3:0]; wire [3:0] srf_waddr_2 = (waddr_2[4]) ? `ZERO4 : waddr_2[3:0]; wire [31:0] srf_wdata_1 = (waddr_1[4]) ? 32'bZ : wdata_1[31:0]; wire [31:0] srf_wdata_2 = (waddr_2[4]) ? 32'bZ : wdata_2[31:0]; wire [127:0] vrf_data_1, vrf_data_2, vrf_data_3, vrf_data_4; wire [3:0] vrf_waddr_1 = (waddr_1[4]) ? waddr_1[3:0] : `ZERO4; wire [3:0] vrf_waddr_2 = (waddr_2[4]) ? waddr_2[3:0] : `ZERO4; wire [127:0] vrf_wdata_1 = (waddr_1[4]) ? wdata_1 : 128'bZ; wire [127:0] vrf_wdata_2 = (waddr_2[4]) ? wdata_2 : 128'bZ; assign rdata_1 = (raddr_1[4]) ? vrf_data_1 : { 96'd0, srf_data_1 }; assign rdata_2 = (raddr_2[4]) ? vrf_data_2 : { 96'd0, srf_data_2 }; assign rdata_3 = (raddr_3[4]) ? vrf_data_3 : { 96'd0, srf_data_3 }; assign rdata_4 = (raddr_4[4]) ? vrf_data_4 : { 96'd0, srf_data_4 }; register_file_32 RF32 ( .raddr_1(raddr_1[3:0]), .raddr_2(raddr_2[3:0]), .raddr_3(raddr_3[3:0]), .raddr_4(raddr_4[3:0]), .rdata_1(srf_data_1), .rdata_2(srf_data_2), .rdata_3(srf_data_3), .rdata_4(srf_data_4), .waddr_1(srf_waddr_1), .waddr_2(srf_waddr_2), .wdata_1(srf_wdata_1), .wdata_2(srf_wdata_2), .reset(reset), .clk(clk) ); register_file_128 RF128 ( .raddr_1(raddr_1[3:0]), .raddr_2(raddr_2[3:0]), .raddr_3(raddr_3[3:0]), .raddr_4(raddr_4[3:0]), .rdata_1(vrf_data_1), .rdata_2(vrf_data_2), .rdata_3(vrf_data_3), .rdata_4(vrf_data_4), .waddr_1(vrf_waddr_1), .waddr_2(vrf_waddr_2), .wdata_1(vrf_wdata_1), .wdata_2(vrf_wdata_2), .reset(reset), .clk(clk) ); endmodule // // REGISTER FILE register_file_32: 16 32-bit regs, 4 read ports, 2 write ports // module register_file_32 ( raddr_1, raddr_2, raddr_3, raddr_4, rdata_1, rdata_2, rdata_3, rdata_4, waddr_1, waddr_2, wdata_1, wdata_2, reset, clk ); input [3:0] raddr_1; input [3:0] raddr_2; input [3:0] raddr_3; input [3:0] raddr_4; output [31:0] rdata_1; output [31:0] rdata_2; output [31:0] rdata_3; output [31:0] rdata_4; input [3:0] waddr_1; input [3:0] waddr_2; input [31:0] wdata_1; input [31:0] wdata_2; input reset; input clk; wire iclk = reset | clk; reg [31:0] m[1:15]; assign rdata_1 = (raddr_1 == 4'd0) ? `ZERO32 : ((raddr_1 == waddr_1) ? wdata_1 : (raddr_1 == waddr_2) ? wdata_2 : m[raddr_1]); assign rdata_2 = (raddr_2 == 4'd0) ? `ZERO32 : ((raddr_2 == waddr_1) ? wdata_1 : (raddr_2 == waddr_2) ? wdata_2 : m[raddr_2]); assign rdata_3 = (raddr_3 == 4'd0) ? `ZERO32 : ((raddr_3 == waddr_1) ? wdata_1 : (raddr_3 == waddr_2) ? wdata_2 : m[raddr_3]); assign rdata_4 = (raddr_4 == 4'd0) ? `ZERO32 : ((raddr_4 == waddr_1) ? wdata_1 : (raddr_4 == waddr_2) ? wdata_2 : m[raddr_4]); always @(posedge iclk) begin if (reset) begin m[1] <= `ZERO32; m[2] <= `ZERO32; m[3] <= `ZERO32; m[4] <= `ZERO32; m[5] <= `ZERO32; m[6] <= `ZERO32; m[7] <= `ZERO32; m[8] <= `ZERO32; m[9] <= `ZERO32; m[10] <= `ZERO32; m[11] <= `ZERO32; m[12] <= `ZERO32; m[13] <= `ZERO32; m[14] <= `ZERO32; m[15] <= `ZERO32; end else begin if (waddr_1 != 4'd0) begin m[waddr_1] <= wdata_1; end if (waddr_2 != 4'd0) begin m[waddr_2] <= wdata_2; end end end endmodule // // REGISTER FILE register_file_128: 16 128-bit regs, 4 read ports, 2 write ports // module register_file_128 ( raddr_1, raddr_2, raddr_3, raddr_4, rdata_1, rdata_2, rdata_3, rdata_4, waddr_1, waddr_2, wdata_1, wdata_2, reset, clk ); input [3:0] raddr_1; input [3:0] raddr_2; input [3:0] raddr_3; input [3:0] raddr_4; output [127:0] rdata_1; output [127:0] rdata_2; output [127:0] rdata_3; output [127:0] rdata_4; input [3:0] waddr_1; input [3:0] waddr_2; input [127:0] wdata_1; input [127:0] wdata_2; input reset; input clk; wire iclk = reset | clk; reg [127:0] m[1:15]; assign rdata_1 = (raddr_1 == 4'd0) ? `ZERO128 : ((raddr_1 == waddr_1) ? wdata_1 : (raddr_1 == waddr_2) ? wdata_2 : m[raddr_1]); assign rdata_2 = (raddr_2 == 4'd0) ? `ZERO128 : ((raddr_2 == waddr_1) ? wdata_1 : (raddr_2 == waddr_2) ? wdata_2 : m[raddr_2]); assign rdata_3 = (raddr_3 == 4'd0) ? `ZERO128 : ((raddr_3 == waddr_1) ? wdata_1 : (raddr_3 == waddr_2) ? wdata_2 : m[raddr_3]); assign rdata_4 = (raddr_4 == 4'd0) ? `ZERO128 : ((raddr_4 == waddr_1) ? wdata_1 : (raddr_4 == waddr_2) ? wdata_2 : m[raddr_4]); always @(posedge iclk) begin if (reset) begin m[1] <= `ZERO128; m[2] <= `ZERO128; m[3] <= `ZERO128; m[4] <= `ZERO128; m[5] <= `ZERO128; m[6] <= `ZERO128; m[7] <= `ZERO128; m[8] <= `ZERO128; m[9] <= `ZERO128; m[10] <= `ZERO128; m[11] <= `ZERO128; m[12] <= `ZERO128; m[13] <= `ZERO128; m[14] <= `ZERO128; m[15] <= `ZERO128; end else begin if (waddr_1 != 4'd0) begin m[waddr_1] <= wdata_1; end if (waddr_2 != 4'd0) begin m[waddr_2] <= wdata_2; end end end endmodule