`define ZERO 32'h0 `define ZERO128 128'h0 // // default: 32 bits ... override parm when instantiated to get different widths // module registerX (reset, clk, in, out, we); parameter width = 32; input reset; input clk; output [width-1:0] out; input [width-1:0] in; input we; reg [width-1:0] m; assign out = m; always @(posedge clk) begin m <= (reset) ? 0 : (we) ? in : m; end endmodule // // PC // module PC ( clk, reset, we, PC_pc__in, PC_pc__out ); input clk; input reset; input we; input [31:0] PC_pc__in; output [31:0] PC_pc__out; registerX #(32) PC_pc (.reset(reset), .clk(clk), .we(we), .out(PC_pc__out), .in(PC_pc__in)); endmodule // // IFID // module IFID ( clk, reset, we, IFID_instr__in, IFID_instr__out ); input clk; input reset; input we; input [31:0] IFID_instr__in; output [31:0] IFID_instr__out; registerX #(32) IFID_instr (.reset(reset), .clk(clk), .we(we), .out(IFID_instr__out), .in(IFID_instr__in)); endmodule // // IDEX // module IDEX ( clk, reset, we, IDEX_arg1__in, IDEX_arg1__out, IDEX_arg2__in, IDEX_arg2__out, IDEX_arg3__in, IDEX_arg3__out, IDEX_op__in, IDEX_op__out, IDEX_rT__in, IDEX_rT__out, IDEX_src1__in, IDEX_src1__out, IDEX_src2__in, IDEX_src2__out ); input clk; input reset; input we; input [127:0] IDEX_arg1__in; output [127:0] IDEX_arg1__out; input [127:0] IDEX_arg2__in; output [127:0] IDEX_arg2__out; input [31:0] IDEX_arg3__in; output [31:0] IDEX_arg3__out; input [4:0] IDEX_op__in; output [4:0] IDEX_op__out; input [4:0] IDEX_rT__in; output [4:0] IDEX_rT__out; input [4:0] IDEX_src1__in; output [4:0] IDEX_src1__out; input [4:0] IDEX_src2__in; output [4:0] IDEX_src2__out; wire clk_0, clk_1, clk_2, clk_3, clk_4, clk_5, clk_6, clk_7, clk_8; buf bufclk0(clk_0, clk), bufclk1(clk_1, clk), bufclk2(clk_2, clk), bufclk3(clk_3, clk), bufclk4(clk_4, clk), bufclk5(clk_5, clk), bufclk6(clk_6, clk), bufclk7(clk_7, clk), bufclk8(clk_8, clk); wire reset_0, reset_1, reset_2, reset_3, reset_4, reset_5, reset_6, reset_7, reset_8; buf bufreset0(reset_0, reset), bufreset1(reset_1, reset), bufreset2(reset_2, reset), bufreset3(reset_3, reset), bufreset4(reset_4, reset), bufreset5(reset_5, reset), bufreset6(reset_6, reset), bufreset7(reset_7, reset), bufreset8(reset_8, reset); wire we_0, we_1, we_2, we_3, we_4, we_5, we_6, we_7, we_8; buf bufwe0(we_0, we), bufwe1(we_1, we), bufwe2(we_2, we), bufwe3(we_3, we), bufwe4(we_4, we), bufwe5(we_5, we), bufwe6(we_6, we), bufwe7(we_7, we), bufwe8(we_8, we); registerX #(128) IDEX_arg1 (.reset(reset_1), .clk(clk_1), .we(we_1), .out(IDEX_arg1__out), .in(IDEX_arg1__in)); registerX #(128) IDEX_arg2 (.reset(reset_2), .clk(clk_2), .we(we_2), .out(IDEX_arg2__out), .in(IDEX_arg2__in)); registerX #(32) IDEX_arg3 (.reset(reset_3), .clk(clk_3), .we(we_3), .out(IDEX_arg3__out), .in(IDEX_arg3__in)); registerX #(5) IDEX_op (.reset(reset_4), .clk(clk_4), .we(we_4), .out(IDEX_op__out), .in(IDEX_op__in)); registerX #(5) IDEX_rT (.reset(reset_5), .clk(clk_5), .we(we_5), .out(IDEX_rT__out), .in(IDEX_rT__in)); registerX #(5) IDEX_src1 (.reset(reset_6), .clk(clk_6), .we(we_6), .out(IDEX_src1__out), .in(IDEX_src1__in)); registerX #(5) IDEX_src2 (.reset(reset_7), .clk(clk_7), .we(we_7), .out(IDEX_src2__out), .in(IDEX_src2__in)); endmodule // // EXWB // module EXWB ( clk, reset, we, EXWB_rfdata__in, EXWB_rfdata__out, EXWB_rT__in, EXWB_rT__out ); input clk; input reset; input we; input [127:0] EXWB_rfdata__in; output [127:0] EXWB_rfdata__out; input [4:0] EXWB_rT__in; output [4:0] EXWB_rT__out; wire clk_0, clk_1, clk_2; buf bufclk0(clk_0, clk), bufclk1(clk_1, clk), bufclk2(clk_2, clk); wire reset_0, reset_1, reset_2; buf bufreset0(reset_0, reset), bufreset1(reset_1, reset), bufreset2(reset_2, reset); wire we_0, we_1, we_2; buf bufwe0(we_0, we), bufwe1(we_1, we), bufwe2(we_2, we); registerX #(128) EXWB_rfdata (.reset(reset_1), .clk(clk_1), .we(we_1), .out(EXWB_rfdata__out), .in(EXWB_rfdata__in)); registerX #(5) EXWB_rT (.reset(reset_2), .clk(clk_2), .we(we_2), .out(EXWB_rT__out), .in(EXWB_rT__in)); endmodule // // PC_EXC // module PC_EXC ( clk, reset, we, PCEXC_pc__in, PCEXC_pc__out, PCEXC_exc__in, PCEXC_exc__out ); input clk; input reset; input we; input [31:0] PCEXC_pc__in; output [31:0] PCEXC_pc__out; input [3:0] PCEXC_exc__in; output [3:0] PCEXC_exc__out; wire clk_0, clk_1, clk_2; buf bufclk0(clk_0, clk), bufclk1(clk_1, clk), bufclk2(clk_2, clk); wire reset_0, reset_1, reset_2; buf bufreset0(reset_0, reset), bufreset1(reset_1, reset), bufreset2(reset_2, reset); wire we_0, we_1, we_2; buf bufwe0(we_0, we), bufwe1(we_1, we), bufwe2(we_2, we); registerX #(32) PCEXC_pc (.reset(reset_0), .clk(clk_0), .we(we_0), .out(PCEXC_pc__out), .in(PCEXC_pc__in)); registerX #(4) PCEXC_exc (.reset(reset_1), .clk(clk_1), .we(we_1), .out(PCEXC_exc__out), .in(PCEXC_exc__in)); endmodule