// // test module for RiSC-32 cpu // `define OP_add 4'd0 `define OP_addi 4'd1 `define OP_and 4'd2 `define OP_mul 4'd3 `define OP_sub 4'd4 `define OP_lw 4'd5 `define OP_sw 4'd6 `define OP_bne 4'd7 `define OP_blz 4'd7 `define OP_vadd 4'd8 `define OP_vsum 4'd9 `define OP_vand 4'd10 `define OP_vmul 4'd11 `define OP_vxor 4'd12 `define OP_vlw 4'd13 `define OP_vmov 4'd14 `define OP_vsw 4'd14 `define OP_jalr 4'd15 `define OP_ext 4'd15 module ops (side, op, op0, str); input side; input [3:0] op; input [3:0] op0; output [4*8:0] str; reg [4*8:0] str; always begin #5 case (op) `OP_add: str = (side & op0 == `OP_vmov) ? "vec" : "add"; `OP_addi: str = (side & op0 == `OP_vmov) ? "vlo" : "addi"; `OP_and: str = (side & op0 == `OP_vmov) ? "vhi" : "and"; `OP_mul: str = "mul"; `OP_sub: str = "sub"; `OP_lw: str = "lw"; `OP_sw: str = "sw"; `OP_bne: str = side ? "blz" : "bne"; `OP_vadd: str = "vadd"; `OP_vsum: str = "vsum"; `OP_vand: str = "vand"; `OP_vmul: str = "vmul"; `OP_vxor: str = "vxor"; `OP_vlw: str = "vlw"; `OP_vmov: str = side ? "vsw" : "vmov"; `OP_jalr: str = "jalr"; default: str = "BAD"; endcase end endmodule module top (); reg clk; reg reset; wire [1:0] mreq1, mreq2, mreq3; wire grant1, grant2, grant3; wire [15:0] maddr; wire [63:0] mdata; RiSC32 cpu1( .clk(clk), .reset(reset), .mreq(mreq1), .grant(grant1), .maddr(maddr), .mdata(mdata)); RiSC32 cpu2( .clk(clk), .reset(reset), .mreq(mreq2), .grant(grant2), .maddr(maddr), .mdata(mdata)); RiSC32 cpu3( .clk(clk), .reset(reset), .mreq(mreq3), .grant(grant3), .maddr(maddr), .mdata(mdata)); main_memory mem( .clk(clk), .reset(reset), .req1(mreq1), .req2(mreq2), .req3(mreq3), .grant1(grant1), .grant2(grant2), .grant3(grant3), .addr(maddr), .data(mdata)); integer cycle = 0; integer i; wire [4*8:0] opstring0, opstring1; ops OP0(.side(1'b0), .op(cpu1.op_0), .op0(4'd0), .str(opstring0)); ops OP1(.side(1'b1), .op(cpu1.op_1), .op0(cpu1.op_0), .str(opstring1)); initial begin reset = 0; clk = 0; #1 reset = 1; #1 clk=1; #1 reset = 0; // cheap & dirty CPUID :D cpu1.RF.RF32.m[15] = 32'd1; cpu2.RF.RF32.m[15] = 32'd2; cpu3.RF.RF32.m[15] = 32'd3; $readmemh("init.dat", mem.m); #10000 $finish; end always begin #5 clk = 0; #5 clk = 1; cycle <= cycle + 1; $display("-----------------------------"); $display("Cycle %d", cycle); $display("-----------------------------"); $display("Top - Fetch Stage:"); $display(" PC: %h %h %h", cpu1.PC_pc__out, cpu3.PC_pc__out, cpu3.PC_pc__out); $display(" fetch instr: %h %h %h", cpu1.MEM_fdata__out, cpu2.MEM_fdata__out, cpu3.MEM_fdata__out); $display(" fetch hit: +%h %h %h", cpu1.MEM_f__hit, cpu2.MEM_f__hit, cpu3.MEM_f__hit); if (1'd0) begin $display(" NextPC choices:"); $display(" bpred address: %h", cpu1.BP_pred__out); $display(" EX jump address: %h (%d)", cpu1.jump_addr, cpu1.idex_has_jump); $display(" EX BR mispredict: %h (%d)", cpu1.idex_pcNext, cpu1.idex_mispredict); end if (1'd0) begin $display("IFID - exc/pc: %h %h", cpu1.IFID_exc__out, cpu1.IFID_pc__out); $display(" IFID.instr: %h (lgim=%d run=%d)", cpu1.IFID_instr__out, cpu1.idex_largeImm, cpu1.Run); $display(" instr0 - %s %h %h %h", opstring0, cpu1.rA_0, cpu1.rB_0, cpu1.rC_0); $display(" instr1 - %s %h %h %h", opstring1, cpu1.rA_1, cpu1.rB_1, cpu1.rC_1); end if (1'd0) begin $display("IDEX - exc/pc: %h %h", cpu1.IDEX_exc__out, cpu1.IDEX_pc__out); $display(" IDEX.op/rT %h %h\t\t\t\t\t%h %h", cpu1.IDEX_op_0__out, cpu1.IDEX_rT_0__out, cpu1.IDEX_op_1__out, cpu1.IDEX_rT_1__out); $display(" IDEX.src/arg1: %h %h\t%h %h", cpu1.IDEX_src1_0__out, cpu1.IDEX_arg1_0__out, cpu1.IDEX_src1_1__out, cpu1.IDEX_arg1_1__out); $display(" IDEX.src/arg2: %h %h\t%h %h", cpu1.IDEX_src2_0__out, cpu1.IDEX_arg2_0__out, cpu1.IDEX_src2_1__out, cpu1.IDEX_arg2_1__out); $display(" IDEX.arg3: %h\t\t\t\t%h", cpu1.IDEX_arg3_0__out, cpu1.IDEX_arg3_1__out); $display(" MEM_re/we/hit: %h %h +%h\t\t\t\t\t%h %h +%h", cpu1.MEM_re_1__in, cpu1.MEM_we_1__in, cpu1.MEM_1__hit, cpu1.MEM_re_2__in, cpu1.MEM_we_2__in, cpu1.MEM_2__hit); end if (1'd0) begin $display("EXWB - exc/pc: %h %h", cpu1.EXWB_exc__out, cpu1.EXWB_pc__out); $display(" EXWB.rT/reslt: %h %h\t%h %h", cpu1.EXWB_rT_0__out, cpu1.EXWB_result_0__out, cpu1.EXWB_rT_1__out, cpu1.EXWB_result_1__out); end // // extra debugging set any of these to "d1" to enable printout // if (1'd0) begin $display("Internal Cache State:"); $display(" i/d addr: %h\t\t%h", cpu1.MEM.IC.addr, cpu1.MEM.DC.addr); $display(" i/d state: %b\t\t%b", cpu1.MEM.IC.state, cpu1.MEM.DC.state); $display(" i/d blocknum: %h\t\t%h", cpu1.MEM.IC.blocknum, cpu1.MEM.DC.blocknum); $display(" i/d tagnum: %h\t\t%h", cpu1.MEM.IC.tagcheck, cpu1.MEM.DC.tagcheck); $display(" i/d valid: %b\t\t%b", cpu1.MEM.IC.valid, cpu1.MEM.DC.valid); $display(" i/d tag: %h\t\t%h", cpu1.MEM.IC.tag, cpu1.MEM.DC.tag); $display(" i/d block: %h\t%h", cpu1.MEM.IC.block, cpu1.MEM.DC.block); $display(" i/d dataword: %h\t%h", cpu1.MEM.IC.dataword, cpu1.MEM.DC.dataword); $display(" i/d hit: %b\t\t%b", cpu1.MEM.IC.hit, cpu1.MEM.DC.hit); end if (1'd0) begin $display("Internal BIU State:"); $display(" fe: -> %b\t\tre/we/vec: -> %b/%b/%b", cpu1.MEM.fe, cpu1.MEM.re, cpu1.MEM.we, cpu1.MEM.vec); $display(" faddr: %h\t\taddr: %h", cpu1.MEM.faddr, cpu1.MEM.addr); $display(" fdata: %h\tdata: %h", cpu1.MEM.fdata, cpu1.MEM.data); $display(" f_hit: + %b\t\thit: + %b", cpu1.MEM.f_hit, cpu1.MEM.hit); $display(" - mreq: %b", cpu1.MEM.mreq); $display(" - grant: %b", cpu1.MEM.grant); $display(" - maddr: %h", cpu1.MEM.maddr); $display(" - mdata: %h", cpu1.MEM.mdata); $display(" state: %b", cpu1.MEM.state); end if (1'd0) begin $display("EX MUXes:"); $display(" MUX_EX_fwd1_0__out: %h", cpu1.MUX_EX_fwd1_0__out); $display(" MUX_EX_fwd2_0__out: %h", cpu1.MUX_EX_fwd2_0__out); $display(" MUX_EX_alu2_0__out: %h", cpu1.MUX_EX_alu2_0__out); $display(" MUX_EX_link_0__out: %h", cpu1.MUX_EX_link_0__out); $display(" MUX_EX_resultMux_0__out: %h", cpu1.MUX_EX_resultMux_0__out); $display(" MUX_EX_fwd1_1__out: %h", cpu1.MUX_EX_fwd1_1__out); $display(" MUX_EX_fwd2_1__out: %h", cpu1.MUX_EX_fwd2_1__out); $display(" MUX_EX_alu2_1__out: %h", cpu1.MUX_EX_alu2_1__out); $display(" MUX_EX_link_1__out: %h", cpu1.MUX_EX_link_1__out); $display(" MUX_EX_resultMux_1__out: %h", cpu1.MUX_EX_resultMux_1__out); end if (1'd0) begin $display("MEM Ports:"); $display(" MEM_re_1__in: %h", cpu1.MEM_re_1__in); $display(" MEM_we_1__in: %h", cpu1.MEM_we_1__in); $display(" MEM_1__hit: %h", cpu1.MEM_1__hit); $display(" MEM_re_2__in: %h", cpu1.MEM_re_2__in); $display(" MEM_we_2__in: %h", cpu1.MEM_we_2__in); $display(" MEM_2__hit: %h", cpu1.MEM_2__hit); $display(" MEM_vec_1__in: %h", cpu1.MEM_vec_1__in); $display(" MEM_vec_2__in: %h", cpu1.MEM_vec_2__in); $display(" MEM_addr_1__in: %h", cpu1.MEM_addr_1__in); $display(" MEM_addr_2__in: %h", cpu1.MEM_addr_2__in); $display(" MEM_data_1__io: %h", cpu1.MEM_data_1__io); $display(" MEM_data_2__io: %h", cpu1.MEM_data_2__io); $display(" MEM_fe__in: %h", cpu1.MEM_fe__in); $display(" MEM_f__hit: %h", cpu1.MEM_f__hit); $display(" MEM_faddr__in: %h", cpu1.MEM_faddr__in); $display(" MEM_fdata__out: %h", cpu1.MEM_fdata__out); end if (1'd0) begin $display("RF Ports:"); $display(" RF_raddr_1__in: %h", cpu1.RF_raddr_1__in); $display(" RF_raddr_2__in: %h", cpu1.RF_raddr_2__in); $display(" RF_raddr_3__in: %h", cpu1.RF_raddr_3__in); $display(" RF_raddr_4__in: %h", cpu1.RF_raddr_4__in); $display(" RF_rdata_1__out: %h", cpu1.RF_rdata_1__out); $display(" RF_rdata_2__out: %h", cpu1.RF_rdata_2__out); $display(" RF_rdata_3__out: %h", cpu1.RF_rdata_3__out); $display(" RF_rdata_4__out: %h", cpu1.RF_rdata_4__out); $display(" RF_waddr_1__in: %h", cpu1.RF_waddr_1__in); $display(" RF_waddr_2__in: %h", cpu1.RF_waddr_2__in); $display(" RF_wdata_1__in: %h", cpu1.RF_wdata_1__in); $display(" RF_wdata_2__in: %h", cpu1.RF_wdata_2__in); end if (1'd0) begin $display("ALU Ports:"); $display(" ALU_op_0__in: %h", cpu1.ALU_op_0__in); $display(" ALU_alu1_0__in: %h", cpu1.ALU_alu1_0__in); $display(" ALU_alu2_0__in: %h", cpu1.ALU_alu2_0__in); $display(" ALU_bus_0__out: %h", cpu1.ALU_bus_0__out); $display(" ALU_op_1__in: %h", cpu1.ALU_op_1__in); $display(" ALU_alu1_1__in: %h", cpu1.ALU_alu1_1__in); $display(" ALU_alu2_1__in: %h", cpu1.ALU_alu2_1__in); $display(" ALU_bus_1__out: %h", cpu1.ALU_bus_1__out); end if (1'd0) begin $display("Branch Resolution Ports:"); $display(" BRTEST_arg1_0__in: %h", cpu1.BRTEST_arg1_0__in); $display(" BRTEST_arg2_0__in: %h", cpu1.BRTEST_arg2_0__in); $display(" BRTEST_bne_out_0__out: %h", cpu1.BRTEST_bne_out_0__out); $display(" BRTEST_arg1_1__in: %h", cpu1.BRTEST_arg1_1__in); $display(" BRTEST_arg2_1__in: %h", cpu1.BRTEST_arg2_1__in); $display(" BRTEST_blz_out_1__out: %h", cpu1.BRTEST_blz_out_1__out); end if (1'd0) begin $display("BPRED Ports:"); $display(" BP_pc__in: %h", cpu1.BP_pc__in); $display(" BP_instr__in: %h", cpu1.BP_instr__in); $display(" BP_pcPrev__in: %h", cpu1.BP_pcPrev__in); $display(" BP_instrPrev__in: %h", cpu1.BP_instrPrev__in); $display(" BP_pred__out: %h", cpu1.BP_pred__out); end if (1'd0) begin $display(" v tag data - Instruction Cache 1"); for (i=0; i<8; i++) begin $display(" %b %h %h", cpu1.MEM.IC.valid_array[i], cpu1.MEM.IC.tag_array[i], cpu1.MEM.IC.block_array[i]); end end if (1'd1) begin $display(" d v tag data - Data Cache 1"); for (i=0; i<8; i++) begin $display(" %b %b %h %h", cpu1.MEM.DC.dirty_array[i], cpu1.MEM.DC.valid_array[i], cpu1.MEM.DC.tag_array[i], cpu1.MEM.DC.block_array[i]); end end if (1'd0) begin $display(" v tag data - Instruction Cache 2"); for (i=0; i<8; i++) begin $display(" %b %h %h", cpu2.MEM.IC.valid_array[i], cpu2.MEM.IC.tag_array[i], cpu2.MEM.IC.block_array[i]); end end if (1'd1) begin $display(" d v tag data - Data Cache 2"); for (i=0; i<8; i++) begin $display(" %b %b %h %h", cpu2.MEM.DC.dirty_array[i], cpu2.MEM.DC.valid_array[i], cpu2.MEM.DC.tag_array[i], cpu2.MEM.DC.block_array[i]); end end if (1'd0) begin $display(" v tag data - Instruction Cache 3"); for (i=0; i<8; i++) begin $display(" %b %h %h", cpu3.MEM.IC.valid_array[i], cpu3.MEM.IC.tag_array[i], cpu3.MEM.IC.block_array[i]); end end if (1'd1) begin $display(" d v tag data - Data Cache 3"); for (i=0; i<8; i++) begin $display(" %b %b %h %h", cpu3.MEM.DC.dirty_array[i], cpu3.MEM.DC.valid_array[i], cpu3.MEM.DC.tag_array[i], cpu3.MEM.DC.block_array[i]); end end if (1'd0) begin $display("Register-File Contents 1:"); $display(" r0 - 00000000 v0 - 00000000000000000000000000000000"); $display(" r1 - %h v1 - %h", cpu1.RF.RF32.m[1], cpu1.RF.RF128.m[1]); $display(" r2 - %h v2 - %h", cpu1.RF.RF32.m[2], cpu1.RF.RF128.m[2]); $display(" r3 - %h v3 - %h", cpu1.RF.RF32.m[3], cpu1.RF.RF128.m[3]); $display(" r4 - %h v4 - %h", cpu1.RF.RF32.m[4], cpu1.RF.RF128.m[4]); $display(" r5 - %h v5 - %h", cpu1.RF.RF32.m[5], cpu1.RF.RF128.m[5]); $display(" r6 - %h v6 - %h", cpu1.RF.RF32.m[6], cpu1.RF.RF128.m[6]); $display(" r7 - %h v7 - %h", cpu1.RF.RF32.m[7], cpu1.RF.RF128.m[7]); $display(" r8 - %h v8 - %h", cpu1.RF.RF32.m[8], cpu1.RF.RF128.m[8]); $display(" r9 - %h v9 - %h", cpu1.RF.RF32.m[9], cpu1.RF.RF128.m[9]); $display(" rA - %h vA - %h", cpu1.RF.RF32.m[10], cpu1.RF.RF128.m[10]); $display(" rB - %h vB - %h", cpu1.RF.RF32.m[11], cpu1.RF.RF128.m[11]); $display(" rC - %h vC - %h", cpu1.RF.RF32.m[12], cpu1.RF.RF128.m[12]); $display(" rD - %h vD - %h", cpu1.RF.RF32.m[13], cpu1.RF.RF128.m[13]); $display(" rE - %h vE - %h", cpu1.RF.RF32.m[14], cpu1.RF.RF128.m[14]); $display(" rF - %h vF - %h", cpu1.RF.RF32.m[15], cpu1.RF.RF128.m[15]); end if (1'd0) begin $display("Register-File Contents 2:"); $display(" r0 - 00000000 v0 - 00000000000000000000000000000000"); $display(" r1 - %h v1 - %h", cpu2.RF.RF32.m[1], cpu2.RF.RF128.m[1]); $display(" r2 - %h v2 - %h", cpu2.RF.RF32.m[2], cpu2.RF.RF128.m[2]); $display(" r3 - %h v3 - %h", cpu2.RF.RF32.m[3], cpu2.RF.RF128.m[3]); $display(" r4 - %h v4 - %h", cpu2.RF.RF32.m[4], cpu2.RF.RF128.m[4]); $display(" r5 - %h v5 - %h", cpu2.RF.RF32.m[5], cpu2.RF.RF128.m[5]); $display(" r6 - %h v6 - %h", cpu2.RF.RF32.m[6], cpu2.RF.RF128.m[6]); $display(" r7 - %h v7 - %h", cpu2.RF.RF32.m[7], cpu2.RF.RF128.m[7]); $display(" r8 - %h v8 - %h", cpu2.RF.RF32.m[8], cpu2.RF.RF128.m[8]); $display(" r9 - %h v9 - %h", cpu2.RF.RF32.m[9], cpu2.RF.RF128.m[9]); $display(" rA - %h vA - %h", cpu2.RF.RF32.m[10], cpu2.RF.RF128.m[10]); $display(" rB - %h vB - %h", cpu2.RF.RF32.m[11], cpu2.RF.RF128.m[11]); $display(" rC - %h vC - %h", cpu2.RF.RF32.m[12], cpu2.RF.RF128.m[12]); $display(" rD - %h vD - %h", cpu2.RF.RF32.m[13], cpu2.RF.RF128.m[13]); $display(" rE - %h vE - %h", cpu2.RF.RF32.m[14], cpu2.RF.RF128.m[14]); $display(" rF - %h vF - %h", cpu2.RF.RF32.m[15], cpu2.RF.RF128.m[15]); end if (1'd0) begin $display("Register-File Contents 3:"); $display(" r0 - 00000000 v0 - 00000000000000000000000000000000"); $display(" r1 - %h v1 - %h", cpu3.RF.RF32.m[1], cpu3.RF.RF128.m[1]); $display(" r2 - %h v2 - %h", cpu3.RF.RF32.m[2], cpu3.RF.RF128.m[2]); $display(" r3 - %h v3 - %h", cpu3.RF.RF32.m[3], cpu3.RF.RF128.m[3]); $display(" r4 - %h v4 - %h", cpu3.RF.RF32.m[4], cpu3.RF.RF128.m[4]); $display(" r5 - %h v5 - %h", cpu3.RF.RF32.m[5], cpu3.RF.RF128.m[5]); $display(" r6 - %h v6 - %h", cpu3.RF.RF32.m[6], cpu3.RF.RF128.m[6]); $display(" r7 - %h v7 - %h", cpu3.RF.RF32.m[7], cpu3.RF.RF128.m[7]); $display(" r8 - %h v8 - %h", cpu3.RF.RF32.m[8], cpu3.RF.RF128.m[8]); $display(" r9 - %h v9 - %h", cpu3.RF.RF32.m[9], cpu3.RF.RF128.m[9]); $display(" rA - %h vA - %h", cpu3.RF.RF32.m[10], cpu3.RF.RF128.m[10]); $display(" rB - %h vB - %h", cpu3.RF.RF32.m[11], cpu3.RF.RF128.m[11]); $display(" rC - %h vC - %h", cpu3.RF.RF32.m[12], cpu3.RF.RF128.m[12]); $display(" rD - %h vD - %h", cpu3.RF.RF32.m[13], cpu3.RF.RF128.m[13]); $display(" rE - %h vE - %h", cpu3.RF.RF32.m[14], cpu3.RF.RF128.m[14]); $display(" rF - %h vF - %h", cpu3.RF.RF32.m[15], cpu3.RF.RF128.m[15]); end if (1'd1) begin $display("Memory Bus:"); $display(" mreq1: %b", mreq1); $display(" grant1: %b", grant1); $display(" mreq2: %b", mreq2); $display(" grant2: %b", grant2); $display(" mreq3: %b", mreq3); $display(" grant3: %b", grant3); $display(" maddr: %h", maddr); $display(" mdata: %h", mdata); end if (1'd1) begin $display("Memory-Controller Internals:"); $display(" mem.cpu = %b", mem.cpu); $display(" mem.active = %b", mem.active_state); $display(" mem.state1 = %b", mem.state[3'd1]); $display(" mem.state2 = %b", mem.state[3'd2]); $display(" mem.state3 = %b", mem.state[3'd3]); $display(" mem.random = %h", mem.random); $display(" mem.data = %h", mem.data); $display(" mem.datareg = %h", mem.datareg); end if (1'd1) begin $display("Memory Contents:"); $display(" 00: %h %h %h %h", mem.m[0], mem.m[1], mem.m[2], mem.m[3]); $display(" 04: %h %h %h %h", mem.m[4], mem.m[5], mem.m[6], mem.m[7]); $display(" 08: %h %h %h %h", mem.m[8], mem.m[9], mem.m[10], mem.m[11]); $display(" 0c: %h %h %h %h", mem.m[12], mem.m[13], mem.m[14], mem.m[15]); $display(" 10: %h %h %h %h", mem.m[16], mem.m[17], mem.m[18], mem.m[19]); $display(" 14: %h %h %h %h", mem.m[20], mem.m[21], mem.m[22], mem.m[23]); $display(" 18: %h %h %h %h", mem.m[24], mem.m[25], mem.m[26], mem.m[27]); $display(" 1c: %h %h %h %h", mem.m[28], mem.m[29], mem.m[30], mem.m[31]); $display(" 20: %h %h %h %h", mem.m[32], mem.m[33], mem.m[34], mem.m[35]); $display(" 24: %h %h %h %h", mem.m[36], mem.m[37], mem.m[38], mem.m[39]); $display(" 28: %h %h %h %h", mem.m[40], mem.m[41], mem.m[42], mem.m[43]); $display(" 2c: %h %h %h %h", mem.m[44], mem.m[45], mem.m[46], mem.m[47]); end if (1'd0) begin $display(" 30: %h %h %h %h", mem.m[48], mem.m[49], mem.m[50], mem.m[51]); $display(" 34: %h %h %h %h", mem.m[52], mem.m[53], mem.m[54], mem.m[55]); $display(" 38: %h %h %h %h", mem.m[56], mem.m[57], mem.m[58], mem.m[59]); $display(" 3c: %h %h %h %h", mem.m[60], mem.m[61], mem.m[62], mem.m[63]); $display(" 40: %h %h %h %h", mem.m[64], mem.m[65], mem.m[66], mem.m[67]); $display(" 44: %h %h %h %h", mem.m[68], mem.m[69], mem.m[70], mem.m[71]); $display(" 48: %h %h %h %h", mem.m[72], mem.m[73], mem.m[74], mem.m[75]); $display(" 4c: %h %h %h %h", mem.m[76], mem.m[77], mem.m[78], mem.m[79]); $display(" 50: %h %h %h %h", mem.m[80], mem.m[81], mem.m[82], mem.m[83]); $display(" 54: %h %h %h %h", mem.m[84], mem.m[85], mem.m[86], mem.m[87]); $display(" 58: %h %h %h %h", mem.m[88], mem.m[89], mem.m[90], mem.m[91]); $display(" 5c: %h %h %h %h", mem.m[92], mem.m[93], mem.m[94], mem.m[95]); $display(" 60: %h %h %h %h", mem.m[96], mem.m[97], mem.m[98], mem.m[99]); $display(" 64: %h %h %h %h", mem.m[100], mem.m[101], mem.m[102], mem.m[103]); $display(" 68: %h %h %h %h", mem.m[104], mem.m[105], mem.m[106], mem.m[107]); $display(" 6c: %h %h %h %h", mem.m[108], mem.m[109], mem.m[110], mem.m[111]); $display(" 70: %h %h %h %h", mem.m[112], mem.m[113], mem.m[114], mem.m[115]); $display(" 74: %h %h %h %h", mem.m[116], mem.m[117], mem.m[118], mem.m[119]); $display(" 78: %h %h %h %h", mem.m[120], mem.m[121], mem.m[122], mem.m[123]); $display(" 7c: %h %h %h %h", mem.m[124], mem.m[125], mem.m[126], mem.m[127]); end end endmodule