ENEE 646: Digital Computer Design by Peter Petrov

Fall 2007

Class Information

Instructor: Peter Petrov, AVW 1421, ppetrov at ece dot umd dot edu; Please, include ENEE646 in the subject line!
Class hours: TuTh 6:30pm - 7:45pm, CHE 2136
Office hours: Open doors and email appointment, AVW 1421
Required text: "Computer Architecture: A Quantitative Approach", Fourth Edition, by John L. Hennessy and David A. Patterson

Course Syllabus

Class evaluation:
Midterm 1 - October 4 (Thursday), in class. 30%
Midterm 2 - November 6 (Tuesday), in class. 30%
Final - December 18 (Tuesday), 6:30p - 8:30p, in class room, 40%

Students who want to work on a project must send the instructor an email stating their commitment on that. The decision must be made (and the email received by the instructor) by midnight October 21 (Sunday). The project replaces Midterm-2 and has the same weight towards the final class grade.

Project topics (Details about the pipeline implementation project have been posted!)

Midterm-1 practice problems [pdf]
Midterm-2 practice problems [pdf]
Final exam practice problems [pdf]
Solutions of problems 4.3, 4.5, and 4.17 from the textbook. [ppt]

Lecture Notes

Introduction. Quantitative Principles of Design. Technology Trends. [slides]
Pipelining. [slides]
Exceptions. FP pipeline. Scheduling. [slides]
Out-of-Order Execution. Dynamic Scheduling with a Scoreboard. [slides]
Dynamic Scheduling with Tomasulo's Algorithm. [slides]
Precise Exceptions and Speculation with Tomasulo's Algorithm. [slides]
Branch Prediction. [slides]
Memory Hierarchy. Cache organizations. [slides]
Virtual Memory. [slides]
Advanced Cache Optimizations. [slides]
Multiple Issue Processors. Detecting Loop-Level Parallelism. Software Pipelining. [slides]
Trace Scheduling. Compiler Speculation. [slides]
Limits to ILP. Simultaneous Multithreading. [slides]
Multiprocessors: Taxonomy, Communication Models, Coherence [slides]
Cache Coherence Protocols; Snoop and Directory-based [slides]
Synchronization. Locks, Spin Locks, Barriers. Memory Consistency Models. [slides]
SMP Performance. The SUN T1 (Niagara) Multiprocessor. [slides]
Vector Computers. [slides]

Extra Readings

Virtual-Address Caches: Problems and Solutions in Uniprocessors, by M. Cekleov and M. Dubois [pdf]
Simultaneous Multithreading: A Platform for Next-Generation Processors, by S. Eggers et al [pdf]
Combining Branch Predictors, by Scott MacFarling [pdf]