// // test module for RiSC-32 cpu // `define OP_add 4'd0 `define OP_addi 4'd1 `define OP_and 4'd2 `define OP_mul 4'd3 `define OP_sub 4'd4 `define OP_lw 4'd5 `define OP_sw 4'd6 `define OP_bne 4'd7 `define OP_blz 4'd7 `define OP_vadd 4'd8 `define OP_vsum 4'd9 `define OP_vand 4'd10 `define OP_vmul 4'd11 `define OP_vxor 4'd12 `define OP_vlw 4'd13 `define OP_vmov 4'd14 `define OP_vsw 4'd14 `define OP_jalr 4'd15 `define OP_ext 4'd15 module ops (side, op, op0, str); input side; input [3:0] op; input [3:0] op0; output [4*8:0] str; reg [4*8:0] str; always begin #5 case (op) `OP_add: str = (side & op0 == `OP_vmov) ? "vec" : "add"; `OP_addi: str = (side & op0 == `OP_vmov) ? "vlo" : "addi"; `OP_and: str = (side & op0 == `OP_vmov) ? "vhi" : "and"; `OP_mul: str = "mul"; `OP_sub: str = "sub"; `OP_lw: str = "lw"; `OP_sw: str = "sw"; `OP_bne: str = side ? "blz" : "bne"; `OP_vadd: str = "vadd"; `OP_vsum: str = "vsum"; `OP_vand: str = "vand"; `OP_vmul: str = "vmul"; `OP_vxor: str = "vxor"; `OP_vlw: str = "vlw"; `OP_vmov: str = side ? "vsw" : "vmov"; `OP_jalr: str = "jalr"; default: str = "BAD"; endcase end endmodule module top (); reg clk; reg reset; RiSC32 cpu(clk, reset); integer cycle = 0; wire [4*8:0] opstring0, opstring1; ops OP0(.side(1'b0), .op(cpu.op_0), .op0(4'd0), .str(opstring0)); ops OP1(.side(1'b1), .op(cpu.op_1), .op0(cpu.op_0), .str(opstring1)); initial begin reset = 0; clk = 0; #1 reset = 1; #1 clk=1; #1 reset = 0; $readmemh("init.dat", cpu.MEM.m); #10000 $finish; end always begin #5 clk = 0; #5 clk = 1; cycle <= cycle + 1; $display("---------------------"); $display("Cycle %d", cycle); $display("---------------------"); $display("Top - Fetch Stage:"); $display(" PC: %h", cpu.PC_pc__out); $display(" NextPC choices:"); $display(" bpred address: %h", cpu.BP_pred__out); $display(" EX jump address: %h (%d)", cpu.jump_addr, cpu.idex_has_jump); $display(" EX BR mispredict: %h (%d)", cpu.idex_pcNext, cpu.idex_mispredict); $display("IFID - Decode Stage:"); $display(" IFID.pc: %h", cpu.IFID_pc__out); $display(" IFID.exc: %h", cpu.IFID_exc__out); $display(" IFID.instr: %h (lim=%d)", cpu.IFID_instr__out, cpu.LGimm); $display(" instr0 - %s %h %h %h", opstring0, cpu.rA_0, cpu.rB_0, cpu.rC_0); $display(" instr1 - %s %h %h %h", opstring1, cpu.rA_1, cpu.rB_1, cpu.rC_1); $display("IDEX - Execute Stage:"); $display(" IDEX.pc: %h", cpu.IDEX_pc__out); $display(" IDEX.exc: %h", cpu.IDEX_exc__out); $display(" IDEX.op_0: %h", cpu.IDEX_op_0__out); $display(" IDEX.rT_0: %h", cpu.IDEX_rT_0__out); $display(" IDEX.src1_0: %h", cpu.IDEX_src1_0__out); $display(" IDEX.arg1_0: %h", cpu.IDEX_arg1_0__out); $display(" IDEX.src2_0: %h", cpu.IDEX_src2_0__out); $display(" IDEX.arg2_0: %h", cpu.IDEX_arg2_0__out); $display(" IDEX.arg3_0: %h", cpu.IDEX_arg3_0__out); $display(" IDEX.op_1: %h", cpu.IDEX_op_1__out); $display(" IDEX.rT_1: %h", cpu.IDEX_rT_1__out); $display(" IDEX.src1_1: %h", cpu.IDEX_src1_1__out); $display(" IDEX.arg1_1: %h", cpu.IDEX_arg1_1__out); $display(" IDEX.src2_1: %h", cpu.IDEX_src2_1__out); $display(" IDEX.arg2_1: %h", cpu.IDEX_arg2_1__out); $display(" IDEX.arg3_1: %h", cpu.IDEX_arg3_1__out); $display("EXWB - Writeback Stage:"); $display(" EXWB.pc: %h", cpu.EXWB_pc__out); $display(" EXWB.exc: %h", cpu.EXWB_exc__out); $display(" EXWB.rT_0: %h", cpu.EXWB_rT_0__out); $display(" EXWB.result_0: %h", cpu.EXWB_result_0__out); $display(" EXWB.rT_1: %h", cpu.EXWB_rT_1__out); $display(" EXWB.result_1: %h", cpu.EXWB_result_1__out); // // extra debugging set any of these to "d1" to enable printout // if (1'd0) begin $display("EX MUXes:"); $display(" MUX_EX_fwd1_0__out: %h", cpu.MUX_EX_fwd1_0__out); $display(" MUX_EX_fwd2_0__out: %h", cpu.MUX_EX_fwd2_0__out); $display(" MUX_EX_alu2_0__out: %h", cpu.MUX_EX_alu2_0__out); $display(" MUX_EX_link_0__out: %h", cpu.MUX_EX_link_0__out); $display(" MUX_EX_resultMux_0__out: %h", cpu.MUX_EX_resultMux_0__out); $display(" MUX_EX_fwd1_1__out: %h", cpu.MUX_EX_fwd1_1__out); $display(" MUX_EX_fwd2_1__out: %h", cpu.MUX_EX_fwd2_1__out); $display(" MUX_EX_alu2_1__out: %h", cpu.MUX_EX_alu2_1__out); $display(" MUX_EX_link_1__out: %h", cpu.MUX_EX_link_1__out); $display(" MUX_EX_resultMux_1__out: %h", cpu.MUX_EX_resultMux_1__out); end if (1'd0) begin $display("MEM Ports:"); $display(" MEM_re_1__in: %h", cpu.MEM_re_1__in); $display(" MEM_re_2__in: %h", cpu.MEM_re_2__in); $display(" MEM_we_1__in: %h", cpu.MEM_we_1__in); $display(" MEM_we_2__in: %h", cpu.MEM_we_2__in); $display(" MEM_vec_1__in: %h", cpu.MEM_vec_1__in); $display(" MEM_vec_2__in: %h", cpu.MEM_vec_2__in); $display(" MEM_addr_1__in: %h", cpu.MEM_addr_1__in); $display(" MEM_addr_2__in: %h", cpu.MEM_addr_2__in); $display(" MEM_data_1__io: %h", cpu.MEM_data_1__io); $display(" MEM_data_2__io: %h", cpu.MEM_data_2__io); $display(" MEM_fe__in: %h", cpu.MEM_fe__in); $display(" MEM_faddr__in: %h", cpu.MEM_faddr__in); $display(" MEM_fdata__out: %h", cpu.MEM_fdata__out); end if (1'd0) begin $display("RF Ports:"); $display(" RF_raddr_1__in: %h", cpu.RF_raddr_1__in); $display(" RF_raddr_2__in: %h", cpu.RF_raddr_2__in); $display(" RF_raddr_3__in: %h", cpu.RF_raddr_3__in); $display(" RF_raddr_4__in: %h", cpu.RF_raddr_4__in); $display(" RF_rdata_1__out: %h", cpu.RF_rdata_1__out); $display(" RF_rdata_2__out: %h", cpu.RF_rdata_2__out); $display(" RF_rdata_3__out: %h", cpu.RF_rdata_3__out); $display(" RF_rdata_4__out: %h", cpu.RF_rdata_4__out); $display(" RF_waddr_1__in: %h", cpu.RF_waddr_1__in); $display(" RF_waddr_2__in: %h", cpu.RF_waddr_2__in); $display(" RF_wdata_1__in: %h", cpu.RF_wdata_1__in); $display(" RF_wdata_2__in: %h", cpu.RF_wdata_2__in); end if (1'd0) begin $display("ALU Ports:"); $display(" ALU_op_0__in: %h", cpu.ALU_op_0__in); $display(" ALU_alu1_0__in: %h", cpu.ALU_alu1_0__in); $display(" ALU_alu2_0__in: %h", cpu.ALU_alu2_0__in); $display(" ALU_bus_0__out: %h", cpu.ALU_bus_0__out); $display(" ALU_op_1__in: %h", cpu.ALU_op_1__in); $display(" ALU_alu1_1__in: %h", cpu.ALU_alu1_1__in); $display(" ALU_alu2_1__in: %h", cpu.ALU_alu2_1__in); $display(" ALU_bus_1__out: %h", cpu.ALU_bus_1__out); end if (1'd0) begin $display("Branch Resolution Ports:"); $display(" BRTEST_arg1_0__in: %h", cpu.BRTEST_arg1_0__in); $display(" BRTEST_arg2_0__in: %h", cpu.BRTEST_arg2_0__in); $display(" BRTEST_bne_out_0__out: %h", cpu.BRTEST_bne_out_0__out); $display(" BRTEST_arg1_1__in: %h", cpu.BRTEST_arg1_1__in); $display(" BRTEST_arg2_1__in: %h", cpu.BRTEST_arg2_1__in); $display(" BRTEST_blz_out_1__out: %h", cpu.BRTEST_blz_out_1__out); end if (1'd0) begin $display("BPRED Ports:"); $display(" BP_pc__in: %h", cpu.BP_pc__in); $display(" BP_instr__in: %h", cpu.BP_instr__in); $display(" BP_pcPrev__in: %h", cpu.BP_pcPrev__in); $display(" BP_instrPrev__in: %h", cpu.BP_instrPrev__in); $display(" BP_pred__out: %h", cpu.BP_pred__out); end $display("Scalar Register Contents:"); $display(" r0 - 00000000"); $display(" r1 - %h", cpu.RF.RF32.m[1]); $display(" r2 - %h", cpu.RF.RF32.m[2]); $display(" r3 - %h", cpu.RF.RF32.m[3]); $display(" r4 - %h", cpu.RF.RF32.m[4]); $display(" r5 - %h", cpu.RF.RF32.m[5]); $display(" r6 - %h", cpu.RF.RF32.m[6]); $display(" r7 - %h", cpu.RF.RF32.m[7]); $display(" r8 - %h", cpu.RF.RF32.m[8]); $display(" r9 - %h", cpu.RF.RF32.m[9]); $display(" rA - %h", cpu.RF.RF32.m[10]); $display(" rB - %h", cpu.RF.RF32.m[11]); $display(" rC - %h", cpu.RF.RF32.m[12]); $display(" rD - %h", cpu.RF.RF32.m[13]); $display(" rE - %h", cpu.RF.RF32.m[14]); $display(" rF - %h", cpu.RF.RF32.m[15]); $display("Vector Register Contents:"); $display(" v0 - 00000000000000000000000000000000"); $display(" v1 - %h", cpu.RF.RF128.m[1]); $display(" v2 - %h", cpu.RF.RF128.m[2]); $display(" v3 - %h", cpu.RF.RF128.m[3]); $display(" v4 - %h", cpu.RF.RF128.m[4]); $display(" v5 - %h", cpu.RF.RF128.m[5]); $display(" v6 - %h", cpu.RF.RF128.m[6]); $display(" v7 - %h", cpu.RF.RF128.m[7]); $display(" v8 - %h", cpu.RF.RF128.m[8]); $display(" v9 - %h", cpu.RF.RF128.m[9]); $display(" vA - %h", cpu.RF.RF128.m[10]); $display(" vB - %h", cpu.RF.RF128.m[11]); $display(" vC - %h", cpu.RF.RF128.m[12]); $display(" vD - %h", cpu.RF.RF128.m[13]); $display(" vE - %h", cpu.RF.RF128.m[14]); $display(" vF - %h", cpu.RF.RF128.m[15]); $display("Memory Contents:"); $display(" 000: %h %h %h %h", cpu.MEM.m[0], cpu.MEM.m[1], cpu.MEM.m[2], cpu.MEM.m[3]); $display(" 004: %h %h %h %h", cpu.MEM.m[4], cpu.MEM.m[5], cpu.MEM.m[6], cpu.MEM.m[7]); $display(" 008: %h %h %h %h", cpu.MEM.m[8], cpu.MEM.m[9], cpu.MEM.m[10], cpu.MEM.m[11]); $display(" 012: %h %h %h %h", cpu.MEM.m[12], cpu.MEM.m[13], cpu.MEM.m[14], cpu.MEM.m[15]); $display(" 016: %h %h %h %h", cpu.MEM.m[16], cpu.MEM.m[17], cpu.MEM.m[18], cpu.MEM.m[19]); $display(" 020: %h %h %h %h", cpu.MEM.m[20], cpu.MEM.m[21], cpu.MEM.m[22], cpu.MEM.m[23]); $display(" 024: %h %h %h %h", cpu.MEM.m[24], cpu.MEM.m[25], cpu.MEM.m[26], cpu.MEM.m[27]); $display(" 028: %h %h %h %h", cpu.MEM.m[28], cpu.MEM.m[29], cpu.MEM.m[30], cpu.MEM.m[31]); $display(" 032: %h %h %h %h", cpu.MEM.m[32], cpu.MEM.m[33], cpu.MEM.m[34], cpu.MEM.m[35]); $display(" 036: %h %h %h %h", cpu.MEM.m[36], cpu.MEM.m[37], cpu.MEM.m[38], cpu.MEM.m[39]); $display(" 040: %h %h %h %h", cpu.MEM.m[40], cpu.MEM.m[41], cpu.MEM.m[42], cpu.MEM.m[43]); $display(" 044: %h %h %h %h", cpu.MEM.m[44], cpu.MEM.m[45], cpu.MEM.m[46], cpu.MEM.m[47]); $display(" 048: %h %h %h %h", cpu.MEM.m[48], cpu.MEM.m[49], cpu.MEM.m[50], cpu.MEM.m[51]); $display(" 052: %h %h %h %h", cpu.MEM.m[52], cpu.MEM.m[53], cpu.MEM.m[54], cpu.MEM.m[55]); $display(" 056: %h %h %h %h", cpu.MEM.m[56], cpu.MEM.m[57], cpu.MEM.m[58], cpu.MEM.m[59]); $display(" 060: %h %h %h %h", cpu.MEM.m[60], cpu.MEM.m[61], cpu.MEM.m[62], cpu.MEM.m[63]); $display(" 064: %h %h %h %h", cpu.MEM.m[64], cpu.MEM.m[65], cpu.MEM.m[66], cpu.MEM.m[67]); $display(" 068: %h %h %h %h", cpu.MEM.m[68], cpu.MEM.m[69], cpu.MEM.m[70], cpu.MEM.m[71]); $display(" 072: %h %h %h %h", cpu.MEM.m[72], cpu.MEM.m[73], cpu.MEM.m[74], cpu.MEM.m[75]); $display(" 076: %h %h %h %h", cpu.MEM.m[76], cpu.MEM.m[77], cpu.MEM.m[78], cpu.MEM.m[79]); $display(" 080: %h %h %h %h", cpu.MEM.m[80], cpu.MEM.m[81], cpu.MEM.m[82], cpu.MEM.m[83]); $display(" 084: %h %h %h %h", cpu.MEM.m[84], cpu.MEM.m[85], cpu.MEM.m[86], cpu.MEM.m[87]); $display(" 088: %h %h %h %h", cpu.MEM.m[88], cpu.MEM.m[89], cpu.MEM.m[90], cpu.MEM.m[91]); $display(" 092: %h %h %h %h", cpu.MEM.m[92], cpu.MEM.m[93], cpu.MEM.m[94], cpu.MEM.m[95]); $display(" 096: %h %h %h %h", cpu.MEM.m[96], cpu.MEM.m[97], cpu.MEM.m[98], cpu.MEM.m[99]); $display(" 100: %h %h %h %h", cpu.MEM.m[100], cpu.MEM.m[101], cpu.MEM.m[102], cpu.MEM.m[103]); $display(" 104: %h %h %h %h", cpu.MEM.m[104], cpu.MEM.m[105], cpu.MEM.m[106], cpu.MEM.m[107]); $display(" 108: %h %h %h %h", cpu.MEM.m[108], cpu.MEM.m[109], cpu.MEM.m[110], cpu.MEM.m[111]); $display(" 112: %h %h %h %h", cpu.MEM.m[112], cpu.MEM.m[113], cpu.MEM.m[114], cpu.MEM.m[115]); $display(" 116: %h %h %h %h", cpu.MEM.m[116], cpu.MEM.m[117], cpu.MEM.m[118], cpu.MEM.m[119]); $display(" 120: %h %h %h %h", cpu.MEM.m[120], cpu.MEM.m[121], cpu.MEM.m[122], cpu.MEM.m[123]); $display(" 124: %h %h %h %h", cpu.MEM.m[124], cpu.MEM.m[125], cpu.MEM.m[126], cpu.MEM.m[127]); end endmodule