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< module RiSC32 (clk, reset, mreq, grant, maddr, mdata);
< 	input	clk;
< 	input	reset;
< 	output	[1:0] mreq;
< 	input	grant;
< 	output	[15:0] maddr;
< 	inout	[63:0] mdata;
---
> module RiSC32 (clk, reset);
> 	input   clk;
> 	input   reset;
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< 	wire		MEM_f__hit;
< 	wire		MEM_1__hit;
< 	wire		MEM_2__hit;
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< 	wire		Pstall = (MEM_fe__in & ~MEM_f__hit)
< 				| ((MEM_re_2__in | MEM_we_2__in) & ~MEM_2__hit);
< 	wire		Run = ~Pstall;
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< 	cache_and_BIU	MEM (	.re(MEM_re_2__in), .we(MEM_we_2__in), .addr(MEM_addr_2__in),
< 				.vec(MEM_vec_2__in), .data(MEM_data_2__io), 
< 					.fe(MEM_fe__in), .faddr(MEM_faddr__in), .fdata(MEM_fdata__out),
< 				.mreq(mreq), .grant(grant), .maddr(maddr), .mdata(mdata),
< 				.f_hit(MEM_f__hit), .hit(MEM_2__hit),
---
> 	SRAM_block	MEM (	.re_1(MEM_re_1__in), .re_2(MEM_re_2__in), .we_1(MEM_we_1__in), 
> 				.we_2(MEM_we_2__in), .addr_1(MEM_addr_1__in), .addr_2(MEM_addr_2__in), 
> 				.vec_1(MEM_vec_1__in), .vec_2(MEM_vec_2__in),
> 				.data_1(MEM_data_1__io), .data_2(MEM_data_2__io), 
> 					.fe_1(MEM_fe__in), .faddr_1(MEM_faddr__in), 
> 					.fdata_1(MEM_fdata__out),
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< 				.clk(clk_PC), .reset(reset_PC), .we(Run));
---
> 				.clk(clk_PC), .reset(reset_PC), .we(we_PC));
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< 				.clk(clk_IFIDpc), .reset(reset_IFIDpc | Pstomp), .we(Run));
---
> 				.clk(clk_IFIDpc), .reset(reset_IFIDpc | Pstomp), .we(we_IFIDpc));
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< 				.clk(clk_IFID), .reset(reset_IFID | Pstomp), .we(Run));
---
> 				.clk(clk_IFID), .reset(reset_IFID | Pstomp), .we(we_IFID));
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< 				.clk(clk_IDEXpc), .reset(reset_IDEXpc | Pstomp | LGimm), .we(Run));
---
> 				.clk(clk_IDEXpc), .reset(reset_IDEXpc | Pstomp | LGimm), .we(we_IDEXpc));
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< 				.clk(clk_IDEX_1), .reset(reset_IDEX_1 | Pstomp | LGimm), .we(Run));
---
> 				.clk(clk_IDEX_1), .reset(reset_IDEX_1 | Pstomp | LGimm), .we(we_IDEX_1));
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< 				.clk(clk_IDEX_2), .reset(reset_IDEX_2 | Pstomp | LGimm), .we(Run));
---
> 				.clk(clk_IDEX_2), .reset(reset_IDEX_2 | Pstomp | LGimm), .we(we_IDEX_2));
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< 				.clk(clk_EXWBpc), .reset(reset_EXWBpc), .we(Run));
---
> 				.clk(clk_EXWBpc), .reset(reset_EXWBpc), .we(we_EXWBpc));
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< 				.clk(clk_EXWB_1), .reset(reset_EXWB_1), .we(Run));
---
> 				.clk(clk_EXWB_1), .reset(reset_EXWB_1), .we(we_EXWB_1));
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< 				.clk(clk_EXWB_2), .reset(reset_EXWB_2), .we(Run));
---
> 				.clk(clk_EXWB_2), .reset(reset_EXWB_2), .we(we_EXWB_2));
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< 	wire	ifid_0_has_mem =	ifid_0_has_lw | ifid_0_has_sw | ifid_0_has_vlw;
< 
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< 	assign	Pstomp = Run & (idex_has_jump | idex_mispredict);
---
> 	assign	Pstomp = idex_has_jump | idex_mispredict;
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< 	assign	LGimm = idex_largeImm & Run;
---
> 	assign	LGimm = idex_largeImm;
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< 		if (ifid_0_has_mem) begin
< 			$display("--------- MAJOR ERROR: IFID-0 has illegal memory opcode ---------");
< 			$display("--------- MAJOR ERROR: IFID-0 has illegal memory opcode ---------");
< 			$display("--------- MAJOR ERROR: IFID-0 has illegal memory opcode ---------");
< 			$display("--------- MAJOR ERROR: IFID-0 has illegal memory opcode ---------");
< 			$display("--------- MAJOR ERROR: IFID-0 has illegal memory opcode ---------");
< 		end